US4680609A
Expired / Lapsed
US
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Structure and fabrication of vertically integrated CMOS logic gates
Assignee: STMicroelectronics NV
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Filing: 1984-09-24
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Granted: 1987-07-14
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Expires: 2004-09-24
Abstract
Abstract A vertically integrated CMOS logic gate has spaced semiconductor layers with control gates located between the layers and insulated from them by gate oxide. Transistors formed in one semiconductor layer are vertically aligned with transistors formed in the other semiconductor layer. Pairs of vertically coincident transistors have common control gates and certain of the pairs have integral drain regions. Transistors in one layer are series connected in an open loop configuration and transistors in the other layer are parallel connected in a closed loop configuration. The logic gate function depends on voltages applied to the common control gates and to the open and closed loops. By the vertical integration, a two-input NAND or NOR gate can be made using less area than that required for two simple MOS transistors.
Inventors
- 👤 Iain D. Calder
- 👤 Thomas W. MacElwee
- 👤 Abdalla A. Naem
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:21
CPC Classifications
H; H10; H10D; H10D88/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
231 words
A vertically integrated MOS logic gate comprising first and second active semiconductor layers, one of the active semiconductor layers having an open loop with a pair of parallel legs and an interconnecting portion extending between said parallel legs, said open loop being formed by at least two transistors, one of said transistors having a source region, a channel region and a drain region positioned along one of said parallel legs and the other of said transistors having a source region, a channel region and a drain region positioned along the other of said parallel legs, and the other active semiconductor layer having at least one closed loop in which are formed a plurality of transistors, the transistors in one semiconductor layer being substantially vertically aligned with respect to transistors in the other semiconductor layer and having respective common control gates located between the layers, each control gate controlling one vertically coincident transistor pair, each transistor in said closed loop having a source and a drain region separated by a channel region, at least one of the vertically aligned transistor pairs having drain regions contacting one another at a contact zone, a first and a second lead connected to the open loop to connect the open loop transistors in series, and a third and a fourth lead connected to the or each close loop to connect the closed loop transistors in parallel.
Claim 2
Dependent Claim
231 words
A vertically integrated MOS logic gate comprising first and second active semiconductor layers, one of the active semiconductor layers having an open loop with a pair of parallel legs and an interconnecting portion extending between said parallel legs, said open loop being formed by at least two transistors, one of said transistors having a source region, a channel region and a drain region positioned along one of said parallel legs and the other of said transistors having a source region, a channel region and a drain region positioned along the other of said parallel legs, and the other active semiconductor layer having at least one closed loop in which are formed a plurality of transistors, the transistors in one semiconductor layer being substantially vertically aligned with respect to transistors in the other semiconductor layer and having respective common control gates located between the layers, each control gate controlling one vertically coincident transistor pair, each transistor in said closed loop having a source and a drain region separated by a channel region, at least one of the vertically aligned transistor pairs having drain regions contacting one another at a contact zone, a first and a second lead connected to the open loop to connect the open loop transistors in series, and a third and a fourth lead connected to the or each close loop to connect the closed loop transistors in parallel.
Claim 3
Dependent Claim
24 words
A vertically integrated MOS logic gate as claimed in claim 1 in which the second and the fourth leads form a common output lead.
Claim 4
Dependent Claim
27 words
A vertically integrated MOS logic gate as claimed in claim 2 in which the output lead is connected to the loops at or near the contact zone.
Claim 5
Dependent Claim
37 words
A vertically integrated MOS logic gate as claimed in claim 1 in which the first semiconductor layer is a top layer within a semiconductor substrate and the second semiconductor layer is a film of recrystallized polycrystalline material.
Claim 6
Dependent Claim
17 words
A vertically integrated MOS logic gate as claimed in claim 4 in which the semiconductor is silicon.
Claim 7
Dependent Claim
29 words
A vertically integrated MOS logic gate as claimed in claim 1 in which the open loop is configured as a U-shape and the or each closed loop is rectangular.
Claim 8
Dependent Claim
38 words
A vertically integrated MOS logic gate as claimed in claim 1, the logic gate having multiple inputs, the open loop having a rectangular serpentine configuration and a plurality of such closed loops being configured as a ladder formation.
Claim 9
Dependent Claim
43 words
A vertically integrated MOS logic gate as claimed in claim 1 the logic gate having at least one rectangular closed loop and a U-shaped open loop, opposed limbs of the rectangular loop being vertically aligned with the opposed limbs of the U-shaped loop.
Claim 10
Dependent Claim
28 words
A vertically integrated MOS logic gate as claimed in claim 8 in which the control gates extend orthogonally to the opposed limbs of the U- and rectangular loops.
Claim 11
Dependent Claim
66 words
A vertically integrated MOS logic gate as claimed in claim 1, the logic gate particularly adapted to function as a NAND gate, further comprising means for applying logic input voltages to the respective control gates, means for grounding the first lead, and means for applying a positive logic supply to the third lead, a logic gate output voltage being taken from the second and fourth leads.
Claim 12
Dependent Claim
64 words
A vertically integrated MOS logic gate as claimed in claim 1, the logic gate particularly adapted to function as a NOR gate, further comprising means for applying logic input voltages to respective control gates, means for applying positive logic supply to the first lead and means for grounding the third lead, a logic gate output voltage being taken from the second and fourth leads.
Claim 13
Dependent Claim
32 words
A vertically integrated MOS logic gate as claimed in claim 1 in which p-channel transistors are formed within the first semiconductor layer and n-channel transistors are formed within the second semiconductor layer.
Claim 14
Dependent Claim
32 words
A vertically integrated MOS logic gate as claimed in claim 1 in which n-channel transistors are formed within the first semiconductor layer and p-channel transistors are formed within the second semiconductor layer.
Claim 15
Dependent Claim
28 words
A vertically integrated MOS logic gate as claimed in claim 1 in which the commonly controlled transistors are vertically coincident and the control gates are made of polysilicon.
Claim 16
Dependent Claim
48 words
A vertically integrated MOS logic gate as claimed in claim 1 particularly adapted for multiple inputs, the logic gate having a plurality of the closed loops configured as a ladder, alternating rungs being connected to the third lead and the remaining rungs being connected to the output lead.
Claim 17
Dependent Claim
29 words
A vertically integrated MOS logic gate as claimed in claim 12 in which the second and third leads have portions thereof running parallel to uprights of the ladder configuration.
Claim 18
Dependent Claim
110 words
A vertically integrated MOS logic gate as claimed in claim 1 the gate particularly adapted for multiple inputs, a plurality of the closed loops being arranged in a ladder configuration with one upright of the ladder connected to the second lead means and the other upright of the ladder connected to the third lead means, the open loop extending in a serpentine fashion back and forth across the ladder configured closed loops, cross parts of the serpentine configuration being coincident with the rung parts of the ladder configuration and having vertically aligned transistors formed thereat, the control gates having end portions extending perpendicular to the respective rungs and cross pieces.
Claim 19
Dependent Claim
38 words
A vertically integrated MOS logic gate as claimed in claim 1 in which the lead means are regions of doped polysilicon formed from a layer of polysilicon integral with the loop or loops formed within the semiconductor film.
Claim 20
Dependent Claim
25 words
A vertically integrated MOS logic gate as claimed in claim 1 in which each control gate extends substantially perpendicularly to one of said parallel legs.
References Cited (Backward Citations)
US3967988A
Cited
US4555721A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-13 | 1991-01-12 | 1991-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-13 | 1995-01-12 | 1995-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-13 | 1999-01-12 | 1999-07-14 | $7700.00 | Window Closed / Lapsed |