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US5029324A
Expired / Lapsed
US
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Semiconductor device having a semiconductive protection layer
Assignee: Toshiba Corp
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Filing: 1990-04-16
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Granted: 1991-07-02
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Expires: 2010-04-16
Abstract
Abstract A semiconductor device has a semiconductor region, an electrode layer formed over the semiconductor region, and a protection layer formed to cover the semiconductor region and the electrode layer. In the semiconductor device, the protection layer is a semiconductor protection layer. Part of the semiconductive protection layer is formed thin so as to have a low resistance, permitting a corresponding portion of the electrode layer to be connected to an external bonding wire.
Inventors
- 👤 Akihiko Osawa
- 👤 Yutaka Koshino
- 👤 Yoshiro Baba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:56
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/118; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10W74/00; H10W74/40; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W72/551; H10W72/552; H10W72/59; H10W72/90; H10W72/931; H10W72/934; H10W72/951; H10W72/952; H10W72/953
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
146 words
A semiconductor device comprising: an active semiconductor layer; an electrode layer formed over said active semiconductor layer; and a semiconductive protection layer means for covering said semiconductor active layer and said electrode layer, said semiconductor protection layer means having a substantially uniform composition and including at least one portion of thin cross section having a lower resistance in a thickness direction, relative to a resistance in a surface direction perpendicular to said thickness direction, for electrically connecting said electrode layer to an external element through the thin portion, a thickness of the thin portion being selected to provide a sufficiently low resistance in said thickness direction to enable electrical connection to said electrode layer and said resistance in said surface direction having a value sufficient to prevent flow of current along said surface direction and within a range of 10 7 Ωcm to 10 8 Ωcm.
Claim 2
Dependent Claim
146 words
A semiconductor device comprising: an active semiconductor layer; an electrode layer formed over said active semiconductor layer; and a semiconductive protection layer means for covering said semiconductor active layer and said electrode layer, said semiconductor protection layer means having a substantially uniform composition and including at least one portion of thin cross section having a lower resistance in a thickness direction, relative to a resistance in a surface direction perpendicular to said thickness direction, for electrically connecting said electrode layer to an external element through the thin portion, a thickness of the thin portion being selected to provide a sufficiently low resistance in said thickness direction to enable electrical connection to said electrode layer and said resistance in said surface direction having a value sufficient to prevent flow of current along said surface direction and within a range of 10 7 Ωcm to 10 8 Ωcm.
Claim 3
Dependent Claim
20 words
A semiconductor device according to claim 1, wherein said amorphorus SiC film contains impurity doped to control the resistivity thereof.
Claim 4
Dependent Claim
39 words
A semiconductor device according to claim 2, wherein said semiconductor protection layer means is formed of an amorphous SiC film and the thickness of said amorphous SiC film is set within a range of 0.2 μm to 3 μm.
Claim 5
Dependent Claim
18 words
A semiconductor device according to claim 1, wherein said semiconductive layer means is substantially free from added impurities.
Claim 6
Dependent Claim
20 words
A semiconductor device according to claim 4, wherein said semiconductor protection layer means is formed of an amorphous SiC film.
Claim 7
Dependent Claim
27 words
A semiconductor device according to claim 4, wherein the thickness of said semiconductive protection layer means is set within a range of 0.2 μm to 3 μm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |