Cross-point contact-free floating-gate memory array with silicided buried bitlines

Claim 1

A non-volatile memory cell array, comprising: a plurality of parallel conductors including source-drain regions formed in a face of a semiconductor substrate, each of said conductors being a heavily-doped region of second conductivity-type opposite that of a first conductivity type of the underlying material of said semiconductor substrate, each of said source-drain regions being spaced from at least one other said source-drain region on said face by a channel area; thick field oxide regions located at the face of said semiconductor substrate between adjacent ones of said conductors and between adjacent ones of said channel areas; a floating gate over each said channel area, the floating gate being separated from said channel area of said face by a gate insulator layer, wherein said floating gate extends over a part of each adjacent thick field oxide region, the extensions being in directions substantially at right angles to the direction of said parallel conductors; a control gate extending along said face over said floating gate, the control gate being separated from said floating gate by an inter-level dielectric layer; and a plurality of separately formed wordlines contacting said control gates and extending over said control gates in a direction substantially at right angle to the direction of said parallel conductors; wherein each of said conductors including said source-drain regions also includes a silicided region.