Multiple page programmable logic architecture

Claim 1

A logic array circuit comprising: a plurality of L input leads for receiving a plurality of input signals, where L is a first positive integer; a set of N first logic arrays, where N is a second positive integer greater than or equal to one, each of said N first logic arrays including means for receiving signals related to selected ones of said input signals, a plurality of P output signal leads, a plurality of logic gates for providing P output signals on said P signal leads as a function of said signals related to selected ones of said input signals, where P is a third positive integer associated with that one of said N first logic arrays; means for storing a first plurality of pages of information defining desired logic configuration patterns; and first means for downloading said information from a selected one or more of said first plurality of pages to said set of N first logic arrays, thereby configuring said set of N first logic arrays to perform one or more logical functions.