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US5010552A
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US
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Device and method for the generation of test vectors and testing method for integrated circuits
Assignee: Thales SA
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Filing: 1987-10-08
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Granted: 1991-04-23
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Expires: 2007-10-08
Abstract
Abstract A device and a method are used to test integrated circuits, especially P.L.A.s. The possible faults of a circuit to be tested are determined including logic faults caused by the physical structure and relative position of the circuit elements in the integrated logic circuit. On the basis of the faults, a set of test vectors is determined, each fault modifying at least one of the test vectors applied to the circuit to be tested. It is possible to use test vectors which are modified by the greatest number of possible faults. By determining the test vectors on the basis of the faults which are to be detected, the tests can use a small number of vectors while, at the same time, there is certainty that it will be possible to detect all the faults in a given circuit. Advantageously, a hierarchically-organized set of cells is determined with certain cells consisting of small cells. The method and device can be used to test P.L.A.s by using a small number of test vectors, and are applicable to testing integrated circuits and P.L.A.s.
Inventors
- 👤 Bernard Dias
- 👤 Arnaud du Chene
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:46
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318321; G01R31/3185; G01R31/318516
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
172 words
A method of testing each of a series of integrated logic circuits comprising (FIG. 54) the steps of analyzing (60) each type of integrated circuit and determining (61) possible logic faults therein including logic faults caused by the physical structure and relative position of the circuit elements in the integrated logic circuit and how each such logic fault would affect outputs expected to be triggered from said integrated logic circuit by a particular pattern of inputs; generating (63) and applying to inputs of each circuit at least one test vector per possible logic fault so that said vector applied to said logic circuit will trigger at least one actual output pattern which will reveal the existence of any such logic fault; comparing the actual pattern of outputs from said integrated logic circuit with said expected outputs, and indicating, for each integrated logic circuit tested, whether said actual and expected output patterns match; wherein the fault-determining step comprises the step of determining (62) cells logically equivalent to actual parts of the integrated circuit.
Claim 2
Independent Claim
172 words
A method of testing each of a series of integrated logic circuits comprising (FIG. 54) the steps of analyzing (60) each type of integrated circuit and determining (61) possible logic faults therein including logic faults caused by the physical structure and relative position of the circuit elements in the integrated logic circuit and how each such logic fault would affect outputs expected to be triggered from said integrated logic circuit by a particular pattern of inputs; generating (63) and applying to inputs of each circuit at least one test vector per possible logic fault so that said vector applied to said logic circuit will trigger at least one actual output pattern which will reveal the existence of any such logic fault; comparing the actual pattern of outputs from said integrated logic circuit with said expected outputs, and indicating, for each integrated logic circuit tested, whether said actual and expected output patterns match; wherein the fault-determining step comprises the step of determining (62) cells logically equivalent to actual parts of the integrated circuit.
Claim 3
Dependent Claim
17 words
A method according to claim 1 wherein a test vector is matched with each possible logic fault.
Claim 4
Dependent Claim
16 words
A method according to the claim 1 wherein the integrated circuit tested is a combinational circuit.
Claim 5
Dependent Claim
17 words
A method according to the claim 1 wherein the integrated circuit tested is a programmable logic array.
Claim 6
Dependent Claim
30 words
A method according to claim 1, comprising a step of determining an entire equivalent circuit diagram of the integrated circuit, said equivalent circuit diagram comprising a set of interconnected cells.
Claim 7
Dependent Claim
27 words
A method according to claim 1 wherein the logically equivalent cells are hierarchically organized, and each cell consists of a set of interconnected cells of lesser complexity.
Claim 8
Dependent Claim
62 words
A method according to claim 5 wherein the step of generating and applying a test vector to an integrated circuit, triggers a response which is affected by the presence of any logic fault in said circuit, and each test vector is set up by a conventional test vector generator (74), using the equivalent diagram of said circuit determined in said diagram-determining step.
References Cited (Backward Citations)
FR1512238A
Cited
US3576541A
Cited
US3832535A
Cited
US3961250A
Cited
US4225957A
Cited
US4503538A
Cited
US4517672A
Cited
US4493045A
Cited
US4622647A
Cited
US4692920A
Cited
JPS6042665A
Cited
US4719599A
Cited
US4625311A
Cited
US4672610A
Cited
JPS6243577A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-22 | 1994-10-22 | 1995-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-22 | 1998-10-22 | 1999-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-22 | 2002-10-22 | 2003-04-23 | $7700.00 | Window Closed / Lapsed |