Programmable array logic circuit with testing and verification circuitry

Claim 2

A programmable array logic circuit comprising: a programmable logic array matrix comprising a first programmable logic array followed by a second logic array; said matrix including a plurality of input lines and a plurality of output lines; means for sensing each of the output lines of said logic array matrix to determine the logical state thereof during the operation of the programmed logic circuit; means for allowing a test signal at selected input lines to pass through said programmed logic array matrix; and vertification means for utilizing the same sensing means to sense the effect and speed of the test signals to verify if the logic array has been correctly programmed.

Claim 3

A programmable array logic circuit as in claim 1 wherein said verification means comprises means for determining the logical state of a single output line under its normal operating conditions while at the same time disabling all of the remaining output lines.

Claim 4

A programmable array logic circuit as in claim 2 wherein said sensing means for each output line also performs a logic function to the signals thereon.

Claim 5

A programmable array logic circuit comprising: a programmable logic array matrix comprising a first programmable logic array followed by a second logic array; said matrix including a plurality of input lines and a plurality of m output lines arranged into n subgroups which are connected together to form n circuit outputs; means for sensing each of the n circuit outputs to determine the logical state thereof during the operation of the programmed logic circuit; means for allowing selected test signals at said input lines for passage through said programmed logic array matrix; and verification means for utilizing the same sensing means to sense the effect and/or speed of said test signals to verify if the logic array has been correctly programmed.

Claim 6

A programmable array logic circuit comprising: a programmable logic array matrix comprising a first programmable logic array followed by a second logic array; said matrix including a plurality of input lines and a plurality of m output lines arranged into n subgroups which are connected together to form n circuit outputs; means for sensing each of the n circuit outputs to determine the logical state thereof during the operation of the programmed logic circuit; means for allowing selected test signals at said input lines for passage through said programmed logic array matrix; and verification means for utilizing the same sensing means to sense the effect and/or speed of said test signals to verify if the logic array has been correctly programmed.

Claim 7

A programmable array logic circuit as in claim 4 wherein said verification means comprises means for determining the logical state of a single output line within each of the n subgroups under its normal operating conditions while at the same time disabling all of the remaining output lines within each of the n subgroups.

Claim 8

A programmable array logic circuit as in claim 5 wherein said sensing means for each output line also performs a logic function to the signals thereon.

Claim 9

In a programmable array logic circuit comprising: a programmable logic array matrix, said matrix including a plurality of input and output lines and including a first programmable logic array followed by a second logic array; means for providing selected ones of said output lines as feedback lines to said programmable logic array matrix; a plurality of input buffers, each providing at least four inputs to said logic array matrix, a direct and a feedback input and the logical complement of each; means for sensing each of the output lines to determine the logical state thereof; and wherein the improvement comprises means for a.c. testing an unprogrammed logic array circuit comprising; means for disabling all of said input buffers except one; means for disabling either both true and both complement lines of the single input buffer which is not disabled, thereby leaving only a single unaffected input line to said logic array matrix; means for applying an a.c. signal to said input buffer resulting in a related a.c. signal to a selected input line, the a.c. signal and the related signal having amplitudes and frequencies substantially identical to that used in operation of the logic array circuit after it is programmed; and means for sensing the output of said logic array circuit to measure the time delay between the time a test signal is applied at the input and when its effect appears at the output to test said logic array matrix.

Claim 10

In a programmable array logic circuit comprising: a programmable logic array matrix, said matrix including a plurality of input and output lines and including a first programmable logic array followed by a second logic array; means for providing selected ones of said output lines as feedback lines to said programmable logic array matrix; a plurality of input buffers, each providing at least four inputs to said logic array matrix, a direct and a feedback input and the logical complement of each; means for sensing each of the output lines to determine the logical state thereof; and wherein the improvement comprises means for a.c. testing an unprogrammed logic array circuit comprising; means for disabling all of said input buffers except one; means for disabling either both true and both complement lines of the single input buffer which is not disabled, thereby leaving only a single unaffected input line to said logic array matrix; means for applying an a.c. signal to said input buffer resulting in a related a.c. signal to a selected input line, the a.c. signal and the related signal having amplitudes and frequencies substantially identical to that used in operation of the logic array circuit after it is programmed; and means for sensing the output of said logic array circuit to measure the time delay between the time a test signal is applied at the input and when its effect appears at the output to test said logic array matrix.