Logic network test system with simulator oriented fault test generator

Abstract

Abstract Disclosed is a technique for testing highly complex, functional logic where long sequences of test patterns are needed. A logic network to be tested comprises a large number of logic blocks. The inputs to several of these logic blocks are also the primary inputs (PI) to the logic network to be tested while the output of several of the logic blocks are also outputs (PO) of the logic network to be tested. However, the inputs and outputs of many logic blocks of the network to be tested are inaccessible since as is well known in large scale integration (LSI), a large number of internal circuit nodes cannot be probed directly. In accordance with the present disclosure, such a logic network to be tested is simulated and each of the logic blocks as well as the inputs and outputs of each of these logic blocks is uniquely defined. A first test pattern is then applied to the primary inputs (PI) of the network to set the logic levels on these primary inputs to known values. A particular one of the logic blocks within the network is then selected and a specific fault associated with the particular logic block is assumed. A test value for this assumed specific fault in the simulated network is then propagated towards a primary output, one logic stage at a time, by backtracing through the network to a primary input to determine which primary input value must be altered in order to propagate the assumed fault towards a primary output. Without developing an entire test sequence, analysis at each step determines whether the test is in fact progressing by propagating the test value through the network toward the primary input. The term "test value" is defined as the binary vaue of a point within the logic network that is opposite from that expected in the absence of the assumed fault. When a "test value" has been successfully propagated to a primary output (PO), then it is known that the particular sequence of input test patterns is suitable for detecting the specific fault assumed in the simulator. By applying the same sequence of test patterns to the actual network under test and comparing the primary outputs of the network under test and primary outputs of the simulated network, it is determined whether the particular assumed simulated fault is actually present in the network under test. On a real time basis, each time a successive pattern is applied to the simulated network, it is analyzed, and if found unsuitable, it is discarded and a different changed input pattern is sought by backtracing to a primary input through a different path. Each successive pattern is applied to the network under test only if found to be valid.

Inventors

• 👤 Thomas J. Snethen

Bibliographic Details