Method for fabricating a self-aligned thin-film transistor utilizing planarization and back-side photoresist exposure

Claim 1

A method for fabricating a thin-film transistor, comprising the steps of: (a) forming an opaque gate electrode on a principal surface of a transparent substrate; (b) depositing a first layer of insulation material on the principal substrate surface over the gate electrode; (c) depositing a layer of semiconductor material on the first insulation layer; (d) depositing a second layer of insulation material on the semiconductor layer; (e) selectively etching the second insulation layer to leave a remaining second insulation segment and to expose a portion of the semiconductor layer not covered by the remaining second insulation segment, the remaining second insulation segment being aligned with the gate electrode and being narrower than the gate electrode by a selected overlap distance on each side thereof; (f) depositing a layer of doped semiconductor material on the exposed semiconductor portion and over the remaining second insulation segment; (g) depositing a layer of conductive material on the doped semiconductor material; and (h) selectively etching a portion of the conductive layer and a portion of the doped semiconductor layer to expose at least a top surface of the remaining second insulation segment and to form self-registered source and drain electrodes from the etched conductive layer which each overlap the gate electrode the selected overlap distance, said source and drain electrodes each terminating at said second insulation segment without overlap thereof.

Claim 2

A method for fabricating a thin-film transistor, comprising the steps of: (a) forming an opaque gate electrode on a principal surface of a transparent substrate; (b) depositing a first layer of insulation material on the principal substrate surface over the gate electrode; (c) depositing a layer of semiconductor material on the first insulation layer; (d) depositing a second layer of insulation material on the semiconductor layer; (e) selectively etching the second insulation layer to leave a remaining second insulation segment and to expose a portion of the semiconductor layer not covered by the remaining second insulation segment, the remaining second insulation segment being aligned with the gate electrode and being narrower than the gate electrode by a selected overlap distance on each side thereof; (f) depositing a layer of doped semiconductor material on the exposed semiconductor portion and over the remaining second insulation segment; (g) depositing a layer of conductive material on the doped semiconductor material; and (h) selectively etching a portion of the conductive layer and a portion of the doped semiconductor layer to expose at least a top surface of the remaining second insulation segment and to form self-registered source and drain electrodes from the etched conductive layer which each overlap the gate electrode the selected overlap distance, said source and drain electrodes each terminating at said second insulation segment without overlap thereof.

Claim 6

A method for fabricating a thin-film transistor, comprising the steps of: (a) forming an opaque gate electrode on a principal surface of a transparent substrate; (b) depositing a first layer of insulation material on the principal substrate surface and over the gate electrode; (c) depositing a layer of semiconductor material on the first insulation layer; (d) depositing a second layer of insulation material on the semiconductor layer; (e) depositing a first layer of photoresist on the second insulation layer; (f) exposing a back-side substrate surface, opposite to the principal substrate surface, to UV light for a selected duration, to cause exposure of at least a portion of the first photoresist layer substantially outside of a shadow of the gate electrode; (g) removing at least the exposed first photoresist portion by selective development, to leave a first remaining photoresist portion and to expose a segment of the second insulation layer not covered by the first remaining photoresist portion; (h) selectively etching the second insulation layer segment to leave a remaining second insulation segment, under the first remaining photoresist portion, and to expose a portion of the semiconductor layer not covered by the remaining second insulation segment, the remaining second insulation segment being aligned with the gate electrode and being narrower than the gate electrode by a selected overlap distance on each side thereof; (i) removing the first remaining photoresist portion; (j) depositing a layer of doped semiconductor material on the exposed semiconductor portion and over the remaining second insulation segment; (k) depositing a layer of conductive material on the doped semiconductor material; (l) depositing a planarization layer on the conductive layer; and (m) etching the planarization layer, a portion of the conductive layer and a portion of the doped semiconductor layer, to expose at least a top surface of the remaining second insulation segment, and to form self-registered source and drain electrodes from the etched conductive layer, which each overlap the gate electrode the selected overlap distance.

Claim 7

A method for fabricating a thin-film transistor, comprising the steps of: (a) forming an opaque gate electrode on a principal surface of a transparent substrate; (b) depositing a first layer of insulation material on the principal substrate surface and over the gate electrode; (c) depositing a layer of semiconductor material on the first insulation layer; (d) depositing a second layer of insulation material on the semiconductor layer; (e) depositing a first layer of photoresist on the second insulation layer; (f) exposing a back-side substrate surface, opposite to the principal substrate surface, to UV light for a selected duration, to cause exposure of at least a portion of the first photoresist layer substantially outside of a shadow of the gate electrode; (g) removing at least the exposed first photoresist portion by selective development, to leave a first remaining photoresist portion and to expose a segment of the second insulation layer not covered by the first remaining photoresist portion; (h) selectively etching the second insulation layer segment to leave a remaining second insulation segment, under the first remaining photoresist portion, and to expose a portion of the semiconductor layer not covered by the remaining second insulation segment, the remaining second insulation segment being aligned with the gate electrode and being narrower than the gate electrode by a selected overlap distance on each side thereof; (i) removing the first remaining photoresist portion; (j) depositing a layer of doped semiconductor material on the exposed semiconductor portion and over the remaining second insulation segment; (k) depositing a layer of conductive material on the doped semiconductor material; (l) depositing a planarization layer on the conductive layer; and (m) etching the planarization layer, a portion of the conductive layer and a portion of the doped semiconductor layer, to expose at least a top surface of the remaining second insulation segment, and to form self-registered source and drain electrodes from the etched conductive layer, which each overlap the gate electrode the selected overlap distance.