Patent US5008731A successfully refreshed from Google Patents.
US5008731A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated semiconductor circuit with decoupled D.C. wiring
Assignee: US Philips Corp
•
Filing: 1990-02-16
•
Granted: 1991-04-16
•
Expires: 2010-02-16
Abstract
Abstract An integrated semiconductor circuit, in which the D.C. part of the wiring containing only D.C. information lies on a part of the insulating layer located on the surface which is considerably thinner than the parts of the insulating layer under wiring parts not forming part of the D.C. wiring. Preferably, for this purpose a substrate contact diffusion connected to a reference potential is provided under the D.C. wiring parts. As a result, H.F. interference signals on the D.C. wiring are reduced so that noise and distortion are considerably reduced.
Inventors
- 👤 Robert E. J. Van de Grift
- 👤 Martien van der Veen
- 👤 Andre J. Linssen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
164 words
A monolithic integrated semiconductor circuit comprising a semiconductor body, a semiconductor region adjoining a surface of said semiconductor body and covered with an electrically insulating layer, the semiconductor region including a plurality of semiconductor circuit elements interconnected by conductor tracks disposed on the insulating layer and comprising the wiring of the circuit, said wiring including means for carrying only D.C. information and comprising at least one first conductor track, and said wiring including means for carrying A.C. information and comprising at least one second conductor track, said insulating layer having a first layer portion under only said second conductor track and a second, substantially thinner adjacent layer portion under only said first conductor track and located alongside said first layer portion, said first and second conductor tracks being substantially on different levels, and a connection conductor connected to a part of the semiconductor surface, said second layer portion being located on said part of the semiconductor surface which is connected to said connection conductor.
Claim 2
Dependent Claim
164 words
A monolithic integrated semiconductor circuit comprising a semiconductor body, a semiconductor region adjoining a surface of said semiconductor body and covered with an electrically insulating layer, the semiconductor region including a plurality of semiconductor circuit elements interconnected by conductor tracks disposed on the insulating layer and comprising the wiring of the circuit, said wiring including means for carrying only D.C. information and comprising at least one first conductor track, and said wiring including means for carrying A.C. information and comprising at least one second conductor track, said insulating layer having a first layer portion under only said second conductor track and a second, substantially thinner adjacent layer portion under only said first conductor track and located alongside said first layer portion, said first and second conductor tracks being substantially on different levels, and a connection conductor connected to a part of the semiconductor surface, said second layer portion being located on said part of the semiconductor surface which is connected to said connection conductor.
Claim 3
Dependent Claim
47 words
An integrated semiconductor circuit as claimed in claim 1, characterized in that the second layer portion is located above a highly doped surface zone, which is provided in said semiconductor region and is connected through at least one opening in the insulating layer to said connection conductor.
Claim 4
Dependent Claim
27 words
An integrated semiconductor circuit as claimed in claim 2, characterized in that said highly doped surface zone is of the same conductivity type as said semiconductor region.
Claim 5
Dependent Claim
28 words
An integrated semiconductor circuit as claimed in claim 1, 2 or 3, characterized in that a substantial part of the insulating layer extends outside the first conductor track.
Claim 6
Dependent Claim
43 words
An integrated semiconductor circuit as claimed in claim 1, 2 or 3, characterized in that the thickness of the second layer portion of the insulating layer is less than one third of the thickness of the first layer portion of the insulating layer.
Claim 7
Dependent Claim
36 words
An integrated semiconductor circuit as claimed in claim 1, 2 or 3, characterized in that the thickness of the second layer portion of the insulating layer is at least 10 nm and at most 500 nm.
Claim 8
Dependent Claim
24 words
An integrated semiconductor circuit as claimed in claim 1, 2 or 3, characterized in that said connection conductor is connected to a reference potential.
References Cited (Backward Citations)
US4613883A
Cited
US4656058A
Cited
US4646126A
Cited
US4654689A
Cited
US4796084A
Cited
US4737830A
Cited
US4785202A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-15 | 1994-10-15 | 1995-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-15 | 1998-10-15 | 1999-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-15 | 2002-10-15 | 2003-04-16 | $7700.00 | Window Closed / Lapsed |