Substrate power supply contact for power integrated circuits

Claim 2

An integrated circuit having both logic devices and at least one power switching transistor comprising: a semiconductor substrate of a first conductivity type; isolation regions completely surrounding the logic devices for electrically isolating the logic devices from the power switching transistor wherein the isolation regions are surrounded by a non-isolated area of the substrate; a selectively patterned conductive layer making ohmic contact to at least one area of the logic devices corresponding to a supply contact and making ohmic contact to the non-isolated area of the semiconductor substrate to provide electrical power from the semiconductor substrate to the logic devices when electrical power is supplied to the non-isolated area of the substrate.

Claim 3

The integrated circuit of claim 1, wherein the isolation regions are of a second conductivity type.

Claim 4

The integrated circuit of claim 1 wherein the at least one power switching transistor is a vertical field effect transistor.

Claim 5

An integrated circuit having both logic devices and at least one power switching transistor formed on a substrate, wherein both the logic devices and the power switching transistor are powered by current received from an external power supply which is coupled to the substrate, the power transistor being powered by current flowing from the power supply to the substrate, and the logic devices being powered by current flowing from the power supply through the substrate and through a conductive layer which makes an ohmic contact to the substrate.

Claim 6

An integrated circuit having both logic devices and at least one power switching transistor formed on a substrate, wherein both the logic devices and the power switching transistor are powered by current received from an external power supply which is coupled to the substrate, the power transistor being powered by current flowing from the power supply to the substrate, and the logic devices being powered by current flowing from the power supply through the substrate and through a conductive layer which makes an ohmic contact to the substrate.

Claim 7

The integrated circuit of claim 4 further including at least one area of a same conductivity type as the substrate, formed under the ohmic contact to the substrate for lowering resistance to current flow in the ohmic contact to the substrate.

Claim 8

The integrated circuit of claim 4 further comprising a heatsink that is in electrical contact with the substrate; and a conductive lead which is coupled to the heatsink and extends away from the heatsink, wherein the external power supply is coupled to the heatsink and the conductive lead.

Claim 9

The integrated circuit of claim 4 wherein the at least one power switching transistor is a field effect transistor.

Claim 10

The integrated circuit of claim 6 wherein the at least one power switching transistor is a vertical field effect transistor.

Claim 11

The integrated circuit of claim 4 wherein the logic devices are field effect transistors.

Claim 12

An integrated circuit having both logic devices and at least one power switching transistor comprising: a package with a conductive die mount portion and a conductive lead portion electrically coupled to each other, wherein the package lead portion extends outside the package and is electrically coupled to a power supply; a semiconductor substrate of a first conductivity type and having a first and a second surface; a conductive layer attaching the second surface of the substrate to the package die mount portion; a buried isolation region of a second conductivity type selectively formed on the first surface of the substrate; an epitaxial layer of the first conductivity type, covering the first surface including the buried isolation region; isolation regions of the second conductivity type extending through the epitaxial layer to the buried isolation region, the logic devices being located within an area bounded by both the buried isolation region and the isolation regions which extend through the epitaxial layer, and the at least one power switching transistor being located in an area not bounded by the buried isolation region; a selectively patterned metal layer on the first surface of the epitaxial layer making ohmic contact to at least one of the logic devices and making ohmic contact to at least one area of the semiconductor substrate not bounded by the buried isolation region; whereby current flows from the power supply, through the package die mount portion and lead portion to the semiconductor substrate, and through the semiconductor substrate and the metal layer to the logic devices.

Claim 13

An integrated circuit having both logic devices and at least one power switching transistor comprising: a package with a conductive die mount portion and a conductive lead portion electrically coupled to each other, wherein the package lead portion extends outside the package and is electrically coupled to a power supply; a semiconductor substrate of a first conductivity type and having a first and a second surface; a conductive layer attaching the second surface of the substrate to the package die mount portion; a buried isolation region of a second conductivity type selectively formed on the first surface of the substrate; an epitaxial layer of the first conductivity type, covering the first surface including the buried isolation region; isolation regions of the second conductivity type extending through the epitaxial layer to the buried isolation region, the logic devices being located within an area bounded by both the buried isolation region and the isolation regions which extend through the epitaxial layer, and the at least one power switching transistor being located in an area not bounded by the buried isolation region; a selectively patterned metal layer on the first surface of the epitaxial layer making ohmic contact to at least one of the logic devices and making ohmic contact to at least one area of the semiconductor substrate not bounded by the buried isolation region; whereby current flows from the power supply, through the package die mount portion and lead portion to the semiconductor substrate, and through the semiconductor substrate and the metal layer to the logic devices.

Claim 14

An integrated circuit having both logic devices and at least one power switching transistor comprising: a package with a conductive die mount portion and a conductive lead portion electrically coupled to each other, wherein the package lead portion extends outside the package and is electrically coupled to a power supply; a semiconductor substrate of a first conductivity type and having a first and second surface; a conductive layer attaching the second surface of the substrate to the package die mount portion; a buried isolation region of a second conductivity type selectively formed on the first surface of the substrate; an epitaxial layer of the first conductivity type, covering the first surface including the buried isolation region; isolation regions of the second conductivity type extending through the epitaxial layer to the buried isolation region, the logic devices being located within an area bounded by the buried isolation region, and at least one power switching transistor being located in an area not bounded by the buried isolation region; a selectively patterned metal layer on the first surface of the epitaxial layer making ohmic contact to at least one of the logic devices and making ohmic contact to at least one area of the semiconductor substrate not bounded by the buried isolation regions; whereby current flows from the power supply, through the package die mount portion and lead portion to the semiconductor substrate, and through the semiconductor substrate and the metal layer to the logic devices, wherein the at least one power switching transistor is a vertical field effect transistor having a drain electrode on the second surface of the substrate.

Claim 15

An integrated circuit having both logic devices and at least one power switching transistor comprising: a package with a conductive die mount portion and a conductive lead portion electrically coupled to each other, wherein the package lead portion extends outside the package and is electrically coupled to a power supply; a semiconductor substrate of a first conductivity type and having a first and second surface; a conductive layer attaching the second surface of the substrate to the package die mount portion; a buried isolation region of a second conductivity type selectively formed on the first surface of the substrate; an epitaxial layer of the first conductivity type, covering the first surface including the buried isolation region; isolation regions of the second conductivity type extending through the epitaxial layer to the buried isolation region, the logic devices being located within an area bounded by the buried isolation region, and at least one power switching transistor being located in an area not bounded by the buried isolation region; a selectively patterned metal layer on the first surface of the epitaxial layer making ohmic contact to at least one of the logic devices and making ohmic contact to at least one area of the semiconductor substrate not bounded by the buried isolation regions; whereby current flows from the power supply, through the package die mount portion and lead portion to the semiconductor substrate, and through the semiconductor substrate and the metal layer to the logic devices, wherein the at least one power switching transistor is a vertical field effect transistor having a drain electrode on the second surface of the substrate.