Monolithic integrated semiconductor means to reduce power dissipation of a parasitic transistor

Claim 1

Monolithic integrated semiconductor arrangement including a substrate, an epitaxial layer deposited on one side of the substrate, at least one power diode having an anode and a cathode formed in said epitaxial layer, a first and a second conductor provided on said epitaxial layer, each of the conductors being connected to a different potential when the arrangement is in operation, and the first conductor contacting the cathode, a parasitic transistor whose emitter and base are formed, respectively, by the anode and the cathode of the power diode, and whose collector is formed by the substrate, and a collector path resistance formed by a first part of the substrate below the power diode, said arrangement comprising an isolation diffusion zone formed in said epitaxial layer and connecting said second conductor with said substrate at a connection region remote from said power diode, a second part of the substrate which extends between said connection region and said first substrate part forming an additional collector path resistance laterally connected in series with the first mentioned collector path resistance to reduce collector current flowing through said parasitic transistor.