Semiconductor device

Claim 2

A semiconductor device comprising: (1) an island region of a first type of conductivity selectively formed on a semiconductor substrate of a second conductivity type opposite to the first conductivity type, the island region being electrically connected to a power source; (2) a semiconductor region of the second type of conductivity formed in said island region, said semiconductor region being electrically separated from said semiconductor substrate; (3) an insulating film formed on surfaces of said semiconductor region, said island region and said semiconductor substrate; (4) a bonding pad formed on a portion of said insulating film located over said semiconductor region so that said bonding pad is electrically separated from said semiconductor region; and (5) a bonding wire connected to said bonding pad; wherein said semiconductor region of the second type of conductivity, in plan view, is located, in its entirety, inside of the periphery of the bonding pad that exists over said semiconductor region of the second type of conductivity, so that, in plan view, the entire periphery of the semiconductor region is spaced from, and inside of, the entire periphery of the bonding pad.

Claim 3

A semiconductor device according to claim 1, wherein said island region of the first type of conductivity comprises an n-semiconductor, said semiconductor region of the second type of conductivity comprises a p-semiconductor, and said island region of the first type of conductivity is maintained at the greatest operating potential.

Claim 4

A semiconductor device according to claim 1, further comprising other island regions of the first type of conductivity formed in the substrate, whereby a plurality of island regions of the first type of conductivity are provided in the substrate, said island region of the first type of conductivity being electrically isolated from said other island regions.

Claim 5

A semiconductor device according to claim 1, wherein the bonding pad comprises aluminum, the insulating film comprises a silicon dioxide film, and the semiconductor region of the second type of conductivity comprising a semiconductor region into which impurities are introduced at a high concentration.

Claim 6

A semiconductor device according to claim 1, further comprising a buried layer of the first type of conductivity formed under said island region, said buried layer having an impurity concentration higher than that of said island region.

Claim 7

A semiconductor device according to claim 1, wherein the bonding pad comprises a single metal layer.

Claim 8

A semiconductor device according to claim 5, further comprising at least one semiconductor element formed in said island region of the first type of conductivity, and in a first semiconductor layer of the second type of conductivity that is spaced from said semiconductor region formed below said bonding pad.

Claim 9

A semiconductor device according to claim 7, further including a resistor formed by utilizing said first semiconductor layer of the second type of conductivity.

Claim 10

A semiconductor device according to claim 7, wherein said at least one semiconductor element includes an electrostatic breakdown prevention element, and is comprised of the semiconductor layer of the second type of conductivity formed in said island region of the first type of conductivity and a semiconductor layer of the first type of conductivity formed in said semiconductor layer of the second type of conductivity, and wherein an end of the semiconductor layer of the first type of conductivity serves as an input terminal for receiving signals, and a commonly connected end of said semiconductor layer of the first type of conductivity and said semiconductor layer of the second type of conductivity serves as an output terminal.

Claim 11

A semiconductor device according to claim 1, wherein said semiconductor region of a second type of conductivity is electrically isolated from the island region of the first type of conductivity and floats.

Claim 12

A semiconductor device according to claim 1, further comprising at least one semiconductor element formed in said island region of the first type of conductivity.

Claim 13

A semiconductor device according to claim 1, further comprising a power source means for applying a predetermined potential, and wiring means for applying said predetermined potential from said power source means to said island region of a first type of conductivity.

Claim 14

A semiconductor device according to claim 12, further comprising at least one semiconductor element formed in said island region of the first type of conductivity.

Claim 15

A semiconductor device according to claim 13, wherein said at least one semiconductor element includes at least one semiconductor element using, as a semiconductor region thereof, said island region of a first type of conductivity, so as to apply said predetermined potential to the at least one semiconductor element using the island region as a semiconductor region thereof.

Claim 16

A semiconductor device according to claim 3, wherein the island region of the first type of conductivity is electrically isolate from the other island regions by an isolation layer of the second type of conductivity.

Claim 17

A semiconductor device according to claim 3, further comprising semiconductor elements formed in said other island regions, at least one of the semiconductor elements formed in the other island regions including a region of second type of conductivity, and wherein the depth from the substrate surface of the region of second type of conductivity of the at least one element in the other island regions is substantially equal to the depth from the substrate surface of the semiconductor region of a second type of conductivity formed in the island region.

Claim 18

A semiconductor device according to claim 11, wherein said at least one semiconductor element includes a resistor formed by utilizing a further semiconductor region of the second type of conductivity.

Claim 19

A semiconductor device according to claim 11, wherein said at least one semiconductor element includes an electrostatic breakdown prevention element, and is comprised of a further semiconductor region of the second type of conductivity formed in said island region of the first type of conductivity and a semiconductor region of the first type of conductivity formed in said semiconductor region of the second type of conductivity, and wherein an end of the semiconductor region of the first type of conductivity serves as an input terminal for receiving signals, and a commonly connected end of said semiconductor region of the first type of conductivity and said further semiconductor region of the second type of conductivity serves as an output terminal.

Claim 20

A semiconductor device comprising: (1) an island region of a first type of conductivity formed on a semiconductor substrate of a second type of conductivity opposite to the first type of conductivity, the island region being electricity connected to a power source; (2) a semiconductor region of the second type of conductivity formed in said island region, said semiconductor region being spaced from the semiconductor substrate; (3) an insulating film formed on surfaces of said semiconductor region, said island region and said semiconductor substrate; (4) a bonding pad formed on a portion of said insulating film located over said semiconductor region so that said bonding pad is electrically separated from said semiconductor region; and (5) a bonding wire connected to said bonding pad; wherein said semiconductor region of the second type of conductivity, in plan view, is located, in its entirety, inside of the periphery of the bonding pad that exists over said semiconductor region of the second type of conductivity, so that, in plan view, the entire periphery of said semiconductor region is spaced from, and inside of, the entire periphery of the bonding pad; and wherein said bonding pad includes first and second metal layers, the first metal layer being formed on said insulating film and the second metal layer being formed on the first metal layer.

Claim 21

A semiconductor device comprising: (1) an island region of a first type of conductivity formed on a semiconductor substrate of a second type of conductivity opposite to the first type of conductivity, the island region being electricity connected to a power source; (2) a semiconductor region of the second type of conductivity formed in said island region, said semiconductor region being spaced from the semiconductor substrate; (3) an insulating film formed on surfaces of said semiconductor region, said island region and said semiconductor substrate; (4) a bonding pad formed on a portion of said insulating film located over said semiconductor region so that said bonding pad is electrically separated from said semiconductor region; and (5) a bonding wire connected to said bonding pad; wherein said semiconductor region of the second type of conductivity, in plan view, is located, in its entirety, inside of the periphery of the bonding pad that exists over said semiconductor region of the second type of conductivity, so that, in plan view, the entire periphery of said semiconductor region is spaced from, and inside of, the entire periphery of the bonding pad; and wherein said bonding pad includes first and second metal layers, the first metal layer being formed on said insulating film and the second metal layer being formed on the first metal layer.

Claim 22

A semiconductor device according to claim 19, further comprising an intermediate film formed on the surface of said insulating film and on the surface of the periphery of said first metal layer, said intermediate film extending between the first and second metal layers at the periphery of the first metal layer, the intermediate film including a resin film.

Claim 23

A semiconductor device according to claim 20, wherein the resin film is composed of a polyimide resin.

Claim 24

A semiconductor device comprising: (1) an island region of an n-semiconductor selectively formed on a semiconductor substrate of a p-semiconductor, said island region being maintained at the greatest operating potential; (2) a plurality of semiconductor regions of a p-semiconductor formed in said island region, said plurality of semiconductor regions each being electrically separated from said semiconductor substrate; (3) a buried layer of n-semiconductor formed under said island region, said buried layer having an impurity concentration higher than that of said island region; (4) an insulating film formed on surfaces of said plurality of semiconductor regions, said island region and said semiconductor substrate; (5) respective bonding pads formed on a portion of said insulating film located over said plurality of semiconductor regions so that each of said bonding pads is electrically separated from said plurality of semiconductor regions; (6) bonding wires connected to respective bonding pads; (7) a power source means for applying a predetermined potential, and wiring means for applying said predetermined potential from said power source means to said island region; and (8) at least one semiconductor element formed in said island region of n-semiconductor; said plurality of semiconductor regions of the p-semiconductor, in plan view, is located, in its entirety, inside of the periphery of the bonding pad that exists over a respective semiconductor region of the p-semiconductor, so that, in plan view, the entire periphery of each of the semiconductor regions is spaced from, and inside of, the entire periphery of the respective bonding pad.

Claim 25

A semiconductor device comprising: (1) an island region of an n-semiconductor selectively formed on a semiconductor substrate of a p-semiconductor, said island region being maintained at the greatest operating potential; (2) a plurality of semiconductor regions of a p-semiconductor formed in said island region, said plurality of semiconductor regions each being electrically separated from said semiconductor substrate; (3) a buried layer of n-semiconductor formed under said island region, said buried layer having an impurity concentration higher than that of said island region; (4) an insulating film formed on surfaces of said plurality of semiconductor regions, said island region and said semiconductor substrate; (5) respective bonding pads formed on a portion of said insulating film located over said plurality of semiconductor regions so that each of said bonding pads is electrically separated from said plurality of semiconductor regions; (6) bonding wires connected to respective bonding pads; (7) a power source means for applying a predetermined potential, and wiring means for applying said predetermined potential from said power source means to said island region; and (8) at least one semiconductor element formed in said island region of n-semiconductor; said plurality of semiconductor regions of the p-semiconductor, in plan view, is located, in its entirety, inside of the periphery of the bonding pad that exists over a respective semiconductor region of the p-semiconductor, so that, in plan view, the entire periphery of each of the semiconductor regions is spaced from, and inside of, the entire periphery of the respective bonding pad.

Claim 26

A semiconductor device according to claim 22, wherein said at least one semiconductor element is formed at a portion of said island region between said plurality of semiconductor regions of the p-semiconductor.

Claim 27

A semiconductor device comprising: (1) an island region of an n-semiconductor selectively formed on a semiconductor substrate of a p-semiconductor, said island region being maintained at the greatest operating potential; (2) a semiconductor region of a p-semiconductor formed in said island region, said semiconductor region being electrically separated from said semiconductor substrate; (3) a buried layer of n-semiconductor formed under said island region, said buried layer having an impurity concentration higher than that of said island region; (4) an insulating film formed on surfaces of said semiconductor region, said island region and said semiconductor substrate; (5) a bonding pad formed on a portion of said insulating film located over said semiconductor region so that said bonding pad is electrically separated from said semiconductor region; (6) a bonding wire connected to said bonding pad; (7) a power source means for applying a predetermined potential, and wiring means for applying said predetermined potential from said power source means to said island region; and (8) at least one semiconductor element formed in said island region of an n-semiconductor and in a first semiconductor region of p-semiconductor that is spaced from the semiconductor region formed below the bonding pad; wherein said semiconductor region of the p-semiconductor, in plan view, is located, in its entirety, inside of the periphery of the bonding pad that exists over said semiconductor region of the p-semiconductor, so that, in plan view, the entire periphery of the semiconductor region is spaced from, and inside of, the entire periphery of the bonding pad.

Claim 28

A semiconductor device comprising: (1) an island region of an n-semiconductor selectively formed on a semiconductor substrate of a p-semiconductor, said island region being maintained at the greatest operating potential; (2) a semiconductor region of a p-semiconductor formed in said island region, said semiconductor region being electrically separated from said semiconductor substrate; (3) a buried layer of n-semiconductor formed under said island region, said buried layer having an impurity concentration higher than that of said island region; (4) an insulating film formed on surfaces of said semiconductor region, said island region and said semiconductor substrate; (5) a bonding pad formed on a portion of said insulating film located over said semiconductor region so that said bonding pad is electrically separated from said semiconductor region; (6) a bonding wire connected to said bonding pad; (7) a power source means for applying a predetermined potential, and wiring means for applying said predetermined potential from said power source means to said island region; and (8) at least one semiconductor element formed in said island region of an n-semiconductor and in a first semiconductor region of p-semiconductor that is spaced from the semiconductor region formed below the bonding pad; wherein said semiconductor region of the p-semiconductor, in plan view, is located, in its entirety, inside of the periphery of the bonding pad that exists over said semiconductor region of the p-semiconductor, so that, in plan view, the entire periphery of the semiconductor region is spaced from, and inside of, the entire periphery of the bonding pad.