US4997792A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for separation of diode array chips during fabrication thereof
Assignee: Eastman Kodak Co
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Filing: 1989-11-21
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Granted: 1991-03-05
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Expires: 2009-11-21
Abstract
Abstract Rather than being separated along a single cleavage line between their adjacent ends, diode arrays are spaced apart on a fabrication wafer to allow parallel cleavage lines to be established between the ends of each adjacent pair of arrays by scribed grooves located along opposite sides of a narrow disposable strip of water material. A cleaving technique substantially insures that any projecting lip along the cleavage plane will be on the disposable strip rather than on a diode chip, so that such a defect cannot interfere with proper end-to-end spacing of the chips when they are subsequently assembled to provide a continuous row of chips with uniformly spaced individual light-emitting sites.
Inventors
- 👤 Scott D. McClurg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 02:37
CPC Classifications
H; H10; H10H; H10H29/00; H10H29/10; H10H29/14; H10P; H10P52/00; H10H20/00; H10H20/01; Y; Y10; Y10T; Y10T225/00; Y10T225/10; Y10T225/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
180 words
A method for producing individual diode array chips comprising the steps of: supporting a fabrication wafer having a plurality of diode array areas each of which includes a central row of uniformly spaced diode sites extending between its opposite ends, said diode array areas being arranged on said wafer in multiple rows and columns, said columns being spaced apart to provide disposable regions between the endmost diode sites of the corresponding diode areas, said regions being at least as wide as the thickness of said wafer; scribing parallel cleavage grooves along opposite sides of said regions between the confronting ends of the corresponding diode array areas to establish parallel spaced cleavage lines spaced from the respective endmost diode sites of said diode array areas by no more than half the distance between adjacent diode sites along said central rows thereof, said cleavage lines defining opposite edges of disposable strip regions of said wafer material; and fracturing said wafer material along said cleavage lines to separate the ends of said diode array areas from the corresponding disposable strips of wafer material.
Claim 2
Independent Claim
180 words
A method for producing individual diode array chips comprising the steps of: supporting a fabrication wafer having a plurality of diode array areas each of which includes a central row of uniformly spaced diode sites extending between its opposite ends, said diode array areas being arranged on said wafer in multiple rows and columns, said columns being spaced apart to provide disposable regions between the endmost diode sites of the corresponding diode areas, said regions being at least as wide as the thickness of said wafer; scribing parallel cleavage grooves along opposite sides of said regions between the confronting ends of the corresponding diode array areas to establish parallel spaced cleavage lines spaced from the respective endmost diode sites of said diode array areas by no more than half the distance between adjacent diode sites along said central rows thereof, said cleavage lines defining opposite edges of disposable strip regions of said wafer material; and fracturing said wafer material along said cleavage lines to separate the ends of said diode array areas from the corresponding disposable strips of wafer material.
Claim 3
Dependent Claim
51 words
The method according to claim 1 in which said fracturing is accomplished by applying to said wafer along each of said cleavage lines an asymmetrical cleaving force such that any protrusion along the resulting cleavage plane will tend to develop on said disposable strip rather than on a diode array chip.
Claim 4
Dependent Claim
33 words
The method defined by claim 1 in which said parallel cleavage grooves between the confronting ends of a pair of diode array areas extend less than the entire length of said confronting ends.
Claim 5
Dependent Claim
24 words
The method defined by claim 3 in which said cleavage grooves terminate short of the endmost diode sites of the corresponding diode array areas.
Claim 6
Dependent Claim
45 words
The method defined by claim 2 in which said asymmetrical cleaving force includes a shearing force component acting on said disposable strip region near the corresponding cleavage groove in a direction from the grooved face of said wafer toward the opposite face of said wafer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-04 | 1994-09-03 | 1995-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-04 | 1998-09-03 | 1999-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-04 | 2002-09-03 | 2003-03-05 | $7700.00 | Window Closed / Lapsed |