Patent US4997775A successfully refreshed from Google Patents.
US4997775A
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US
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Method for forming a complementary bipolar transistor structure including a self-aligned vertical PNP transistor
Assignee: International Business Machines Corp
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Filing: 1990-02-26
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Granted: 1991-03-05
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Expires: 2010-02-26
Abstract
Abstract A method of forming a complementary bipolar transistor device includes the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollar region in a first of the device regions; forming an N-type buried subcollector region in a second of the device regions; forming an N-type base region in the common surface of the first device region; forming a layer of P-doped polysilicon over the base region in the first device region and over the second device region; patterning the layer of P-doped polysilicon to form an emitter contact generally centered on the base region of the first device region and a generally annular base contact on the second device region; forming a layer of insulating material over the patterned layer of P-doped polysilicon; forming a layer of N-doped polysilicon generally conformally over the device; patterning the layer of N-doped polysilicon to form a base contact generally surrounding the emitter contact on the first device region and an emitter contact generally surrounded by the base contact on the second device region; and heating the device at least once to drive impurities from the base and emitter contacts on the first and second device regions into the device regions whereby to form a vertical PNP transistor in the first device region and a vertical NPN transistor in the second device region.
Inventors
- 👤 Robert K. Cook
- 👤 Chang-Ming Hsieh
- 👤 Kiyosi Isihara
- 👤 Mario M. Pelella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:32
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/67; H10D84/673; Y; Y10; Y10S; Y10S148/00; Y10S148/011
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
238 words
Method of forming a complementary bipolar transistor device comprising the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollector region in a first of said device regions; forming an N-type buried subcollector region in a second of said device regions; forming an N-type base region in said common surface of said first device region; forming a layer of P-doped polysilicon over said base region in said first device region and over said second device region; patterning said layer of P-doped polysilicon to form an emitter contact generally centered on said base region of said first device region and a generally annular base contact on said second device region; forming a layer of insulating material over the patterned said layer of P-doped polysilicon; forming a layer of N-doped polysilicon generally conformally over the device; patterning said layer of N doped polysilicon to form a base contact generally surrounding said emitter contact on said first device region and an emitter contact generally surrounded by said base contact on said second device region; and heating said device at least once to drive impurities from said base and emitter contacts on said first and second device regions into said device regions whereby to form a vertical PNP transistor in said first device region and a vertical NPN transistor in said second device region.
Claim 2
Dependent Claim
238 words
Method of forming a complementary bipolar transistor device comprising the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollector region in a first of said device regions; forming an N-type buried subcollector region in a second of said device regions; forming an N-type base region in said common surface of said first device region; forming a layer of P-doped polysilicon over said base region in said first device region and over said second device region; patterning said layer of P-doped polysilicon to form an emitter contact generally centered on said base region of said first device region and a generally annular base contact on said second device region; forming a layer of insulating material over the patterned said layer of P-doped polysilicon; forming a layer of N-doped polysilicon generally conformally over the device; patterning said layer of N doped polysilicon to form a base contact generally surrounding said emitter contact on said first device region and an emitter contact generally surrounded by said base contact on said second device region; and heating said device at least once to drive impurities from said base and emitter contacts on said first and second device regions into said device regions whereby to form a vertical PNP transistor in said first device region and a vertical NPN transistor in said second device region.
Claim 3
Dependent Claim
66 words
A method in accordance with claim 1 wherein said step of providing said substrate includes the steps of: providing a P-type semiconductor slab defining a generally planar first surface; epitaxially growing an N-type semiconductor layer over said first surface, said N-type semiconductor layer defining said common surface; and forming isolating regions extending from said common surface into said slab so as to separate said device regions.
Claim 4
Dependent Claim
28 words
A method in accordance with claim 2 and further including the step of epitaxially growing a lightly doped P-type region intermediate said slab and said N-type semiconductor layer.
Claim 5
Dependent Claim
49 words
A method in accordance with claim 2 and further including the step of forming a highly doped N-type buried region in said first device region intermediate said buried subcollector region and said slab, said N-type buried region formed concomitantly with said N-type subcollector region in said second device region.
Claim 6
Dependent Claim
38 words
A method in accordance with claim 4 and further including the step of forming an N-type reachthrough region from the surface of said first device region into contact with said N-type buried region in said first device region.
Claim 7
Dependent Claim
37 words
A method in accordance with claim 1 and further including the step of forming an N-type reachthrough region from the surface of said second device region into contact with said subcollector region in said second device region.
Claim 8
Dependent Claim
39 words
A method in accordance with claim 1 and further including the step of forming a P type reachthrough region from the surface of said first device region into contact with said P-type subcollector region in said first device region.
Claim 9
Dependent Claim
60 words
A method in accordance with claim 1 and further including the steps of: forming a layer of insulating material over the surface of said first and second device regions before performing said step of forming said layer of P-doped polysilicon; and patterning said layer of insulating material to expose a portion of each of said first and second device regions.
Claim 10
Dependent Claim
40 words
A method in accordance with claim 1 wherein said step of forming said insulating layer on the patterned P-doped polysilicon layer includes the step of forming sidewalls of insulating material on the exposed edges of said layer of P-doped polysilicon.
Claim 11
Dependent Claim
38 words
A method in accordance with claim 1 and further including the step of forming a P-type extrinsic base region in said second device region by depositing impurities thereinto after said step of patterning said layer of P-doped polysilicon.
Claim 12
Dependent Claim
70 words
A method in accordance with claim 1 and further including the steps of: removing a portion of the surface of said N-type base region in said first device region to form a recess in said N-type base region; and insulating the wall of said N-type base region formed by said last-recited removing step; whereby said base contact for said first device region is formed at least partially within said recess.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-04 | 1994-09-03 | 1995-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-04 | 1998-09-03 | 1999-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-04 | 2002-09-03 | 2003-03-05 | $7700.00 | Window Closed / Lapsed |