Process for fabricating complementary contactless vertical bipolar transistors

Claim 2

A process for fabricating complementary vertical bipolar transistors on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first epitaxial layer of an opposite conductivity type on said substrate; introducing into a first region of said first epitaxial layer a fast diffusing dopant of the first conductivity type to form a well, and a slower diffusing dopant of the opposite conductivity type to form a buried layer; introducing into a second region of said first epitaxial layer a dopant of the first conductivity type to form a buried layer; forming a second epitaxial layer on said first epitaxial layer; forming respective epitaxial silicon islands in said second epitaxial layer over said first region and said second region; forming a polysilicon emitter transistor of a first type in the epitaxial silicon island over said first region; and forming a polysilicon emitter transistor of a second type in the isolation island over said second region, said transistor of the second type being complementary to said transistor of the first type.

Claim 3

A process as in claim 1, further comprising the step of doping said substrate to achieve a low resistivity.

Claim 4

A process as in claim 2 wherein said fast diffusing dopant is aluminum, further comprising the step of achieving a p-well having a substantially uniform aluminum concentration of 2x10¹⁵ aluminum atoms/cm³ and electrically integrated with said substrate.

Claim 5

A process as in claim 3, further comprising the step of doping said substrate to achieve a resistivity of 0.001 ohm-centimeter.

Claim 6

A process as in claim 1, wherein said first conductivity type is p-type, said opposite conductivity type is n-type, said first transistor type is NPN, and said second transistor type is PNP.

Claim 7

A process for fabricating complementary vertical bipolar transistors on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first epitaxial silicon island underlaid by a buried layer of an opposite conductivity type in a well of the first conductivity type within an epitaxial silicon layer upon said substrate, said well being electrically integrated with said substrate; forming a polysilicon emitter transistor of a first type in said first epitaxial silicon island; forming a second epitaxial silicon island underlaid by a buried layer of the first conductivity type in a region of said epitaxial silicon layer of the opposite conductivity type; and forming a polysilicon emitter transistor of a second type in said second isolation island, said transistor of the second type being complementary to said transistor of the first type.

Claim 8

A process for fabricating complementary vertical bipolar transistors on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first epitaxial silicon island underlaid by a buried layer of an opposite conductivity type in a well of the first conductivity type within an epitaxial silicon layer upon said substrate, said well being electrically integrated with said substrate; forming a polysilicon emitter transistor of a first type in said first epitaxial silicon island; forming a second epitaxial silicon island underlaid by a buried layer of the first conductivity type in a region of said epitaxial silicon layer of the opposite conductivity type; and forming a polysilicon emitter transistor of a second type in said second isolation island, said transistor of the second type being complementary to said transistor of the first type.

Claim 9

A process as in claim 6, wherein said substrate is low resistivity.

Claim 10

A process as in claim 7, wherein said well is a p-well having a substantially uniform aluminum concentration of 2x10¹⁵ atoms/cm³.

Claim 11

A process as in claim 8, wherein the resistivity of said substrate is 0.001 ohm-centimeter.

Claim 12

A process as in claim 6, wherein said first conductivity type is p-type, said opposite conductivity type is n-type, said first transistor type is NPN, and said second transistor type is PNP.

Claim 13

A complementary vertical bipolar transistor structure comprising: a substrate of a first conductivity type; a first epitaxial layer upon said substrate, a first region thereof being of the first conductivity type and electrically integrated with said substrate, and a second region thereof being of an opposite conductivity type; a first epitaxial silicon island defined in a second epitaxial layer over the first region of said first epitaxial layer, said first island being underlaid by a first buried layer of the opposite conductivity type and having a first polysilicon emitter of the opposite conductivity type and a base region of the first conductivity type extending between said first emitter and said first buried layer; and a second epitaxial silicon island defined in said second epitaxial layer over the second region of said first epitaxial layer, said second island being underlaid by a second buried layer of the first conductivity type and having a second polysilicon emitter of the first conductivity type and a base region of the opposite conductivity type extending between said second emitter and said second buried layer.

Claim 14

A complementary vertical bipolar transistor structure comprising: a substrate of a first conductivity type; a first epitaxial layer upon said substrate, a first region thereof being of the first conductivity type and electrically integrated with said substrate, and a second region thereof being of an opposite conductivity type; a first epitaxial silicon island defined in a second epitaxial layer over the first region of said first epitaxial layer, said first island being underlaid by a first buried layer of the opposite conductivity type and having a first polysilicon emitter of the opposite conductivity type and a base region of the first conductivity type extending between said first emitter and said first buried layer; and a second epitaxial silicon island defined in said second epitaxial layer over the second region of said first epitaxial layer, said second island being underlaid by a second buried layer of the first conductivity type and having a second polysilicon emitter of the first conductivity type and a base region of the opposite conductivity type extending between said second emitter and said second buried layer.

Claim 15

A structure as in claim 11, wherein said substrate is highly conductive.

Claim 16

A structure as in claim 11, wherein said first epitaxial region is a p-well.

Claim 17

A structure as in claim 13, wherein said p-well has an aluminum concentration of 2x10¹⁵ atoms/cm³ and said substrate has a resistivity of 0.001 ohms/cm.

Claim 18

A structure as in claim 11, wherein said first conductivity type is p-type and said opposite conductivity type is n-type.

Claim 19

A complementary vertical bipolar transistor structure comprising: a substrate of a first conductivity type; a first epitaxial silicon island defined over an epitaxial region of the first conductivity type formed upon said substrate and electrically integrated therewith, said first epitaxial island being underlaid by a first buried layer of the opposite conductivity type and having a polysilicon emitter of the opposite conductivity type and a base region of the first conductivity type extending between said first emitter and said first buried layer; and a second epitaxial silicon island defined over an epitaxial region of the opposite conductivity type formed upon said substrate, said second island being underlaid by a second buried layer of the first conductivity type and having a second polysilicon emitter of the first conductivity type and a base region of the opposite conductivity type extending between said second emitter and said second buried layer.

Claim 20

A complementary vertical bipolar transistor structure comprising: a substrate of a first conductivity type; a first epitaxial silicon island defined over an epitaxial region of the first conductivity type formed upon said substrate and electrically integrated therewith, said first epitaxial island being underlaid by a first buried layer of the opposite conductivity type and having a polysilicon emitter of the opposite conductivity type and a base region of the first conductivity type extending between said first emitter and said first buried layer; and a second epitaxial silicon island defined over an epitaxial region of the opposite conductivity type formed upon said substrate, said second island being underlaid by a second buried layer of the first conductivity type and having a second polysilicon emitter of the first conductivity type and a base region of the opposite conductivity type extending between said second emitter and said second buried layer.

Claim 21

A structure as in claim 16, wherein said substrate is highly conductive.

Claim 22

A structure as in claim 16, wherein said epitaxial region of the first conductivity type is a p-well.

Claim 23

A structure as in claim 18, wherein said p-well has an aluminum concentration of 2x10¹⁵ atoms/cm³ and said substrate has a resistivity of 0.001 ohms/cm.

Claim 24

A structure as in claim 16, wherein said first conductivity type is p-type and said opposite conductivity type is n-type.