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US3665266A Expired / Lapsed US ⏱️ 0.0 years remaining

Low saturation resistance,low offset voltage,monolithic analog switch

Assignee: Motorola Solutions Inc
•
Filing: 1970-12-10
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Granted: 1972-05-23
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Expires: 1990-12-10
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Abstract

Abstract A low saturation resistance, very low offset voltage, monolithic, analog switch is provided which has high impedance in the off state; this switch being produced by fabricating a transistor on a chip. The transistor is adapted to have its base collector junction forward biased and its emitter base junction reverse biased. The parasitic action of a further transistor including the base and the collector of the inversely biased transistor and the substrate on which the inversely biased transistor is deposited, is eliminated. The inverse beta of the transistor switch is increased, and also the distributed current crowding effects in the so provided transistor is minimized.

Inventors

  • 👤 Kenneth Paul Drozdowicz
  • 👤 William Rey Fowler
  • 👤 George Averkiou

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 20:17
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; H10D; H10D99/00; H10W15/00; H10W15/01

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 262 words
A monolithic semiconductor device structure capable of operation as an analog switch with low saturation resistance and very low offset voltage in the on state and high impedance in the off state comprising a first conductivity type substrate; a second conductivity type epitaxial layer on said substrate; a buried layer region of the second conductivity type selectively positioned between said epitaxial layer and said substrate; and isolation diffusion of said first conductivity type extending from the upper surface of said epitaxial layer through said epitaxial layer, contacting said substrate and completely surrounding and isolating said epitaxial layer from other portions of said substrate; a plurality of annular second conductivity type wall regions within said isolation diffusions extending from the upper surface of said buried layer region so as to form a plurality of tubs of second conductivity type epitaxial material, said buried layer region and said wall regions having a higher conductivity then said epitaxial material; a first conductivity type base region diffused within each of said tubs defining the base of the transistor and a second conductivity type emitter regions substantially filling said base regions except for portions surrounding areas of the base region which extend to the surfAce, said emitter region having a higher conductivity then said buried layer and said epitaxial material; said base material which extends to the surface and surrounded by said emitter region serving as the base contact for the device whereby said device has an offset voltage of less then one hundredth of a volt and an inverse saturation resistance of less then 5 ohms.
Claim 2
Dependent Claim 262 words
A monolithic semiconductor device structure capable of operation as an analog switch with low saturation resistance and very low offset voltage in the on state and high impedance in the off state comprising a first conductivity type substrate; a second conductivity type epitaxial layer on said substrate; a buried layer region of the second conductivity type selectively positioned between said epitaxial layer and said substrate; and isolation diffusion of said first conductivity type extending from the upper surface of said epitaxial layer through said epitaxial layer, contacting said substrate and completely surrounding and isolating said epitaxial layer from other portions of said substrate; a plurality of annular second conductivity type wall regions within said isolation diffusions extending from the upper surface of said buried layer region so as to form a plurality of tubs of second conductivity type epitaxial material, said buried layer region and said wall regions having a higher conductivity then said epitaxial material; a first conductivity type base region diffused within each of said tubs defining the base of the transistor and a second conductivity type emitter regions substantially filling said base regions except for portions surrounding areas of the base region which extend to the surfAce, said emitter region having a higher conductivity then said buried layer and said epitaxial material; said base material which extends to the surface and surrounded by said emitter region serving as the base contact for the device whereby said device has an offset voltage of less then one hundredth of a volt and an inverse saturation resistance of less then 5 ohms.
Claim 3
Dependent Claim 38 words
The invention of claim 1 in which said collector and emitter are of N type semiconductive material and in which said collector, emitter, base, collector contact rings and buried layers are on a substrate of P type material.
Claim 4
Dependent Claim 34 words
The invention of claim 1 in which a ring of the same conductivity type as said base closely surrounds said base region, said last mentioned ring being of higher conductivity than said base region.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-05-23 1975-11-22 1976-05-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-05-23 1979-11-22 1980-05-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-05-23 1983-11-22 1984-05-23 $7700.00 Window Closed / Lapsed

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