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US4994409A
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Method for manufacturing a trench capacitor using a photoresist etch back process
Assignee: SK Hynix Inc
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Filing: 1989-07-18
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Granted: 1991-02-19
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Expires: 2009-07-18
Abstract
Abstract A method for manufacturing a trench capacitor in a silicon wafer using a photoresist etch back process comprising sequentially depositing an oxide layer, a nitride layer and an oxide layer as a mask layer on the Si wafer and coating the mask layer with a photoresist layer is disclosed. A first pattern is formed by removing a portion of the photoresist layer and a second a mask pattern is formed by removing the exposed mask layer along the photoresist pattern, and then completely removing the photoresist. A trench is formed in the Si wafer along the second mask pattern. A thin doped oxide layer having a constant thickness is deposited outside and inside the trench. The doped oxide layer is entirely coated with a photoresist, thereby filling the trench with photoresist. The top surface of the photoresist is then planarized. The resulting photoresist coated Si wafer is baked and the photoresist deposited outside and inside the trench is selectively etched back. The doped oxide layer is selectively etched to the photoresist remaining in the trench, together with the oxide layer. The photoresist remaining inside the trench is completely removed. The doped oxide remaining inside the trench is thermally processed, thereby forming a selective doping region along the wall of the trench in the Si wafer.
Inventors
- 👤 Yong H. Yoon
- 👤 Cheol K. Bok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:50
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0387; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047; H10B12/30; H10B12/37; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
202 words
A method for manufacturing a trench capacitor using a photoresist etch back process comprising: providing a silicon wafer; sequentially depositing an oxide layer, a nitride layer and an oxide layer as a mask layer on the Si wafer and coating the mask layer with a photoresist layer, and forming a first mask pattern by removing a portion of the photoresist layer; forming a second mask pattern by removing the exposed mask layer along the photoresist pattern, and removing the photoresist completely; forming a trench in the Si wafer along the second mask pattern; depositing a thin doped oxide layer having a constant thickness outside and inside the trench, entirely coating the doped oxide layer with a photoresist, thereby filling the trench with photoresist, then planarizing the top surface of the photoresist; baking the resulting photoresist coated Si wafer, and selectively etching back the photoresist deposited outside and inside the trench; selectively etching the doped oxide layer to the photoresist remaining in the trench, together with the oxide layer; and completely removing the photoresist remaining inside the trench, and thermal processing the doped oxide inside the trench, thereby forming a selective doping region along the wall of the trench in the Si wafer.
Claim 2
Independent Claim
202 words
A method for manufacturing a trench capacitor using a photoresist etch back process comprising: providing a silicon wafer; sequentially depositing an oxide layer, a nitride layer and an oxide layer as a mask layer on the Si wafer and coating the mask layer with a photoresist layer, and forming a first mask pattern by removing a portion of the photoresist layer; forming a second mask pattern by removing the exposed mask layer along the photoresist pattern, and removing the photoresist completely; forming a trench in the Si wafer along the second mask pattern; depositing a thin doped oxide layer having a constant thickness outside and inside the trench, entirely coating the doped oxide layer with a photoresist, thereby filling the trench with photoresist, then planarizing the top surface of the photoresist; baking the resulting photoresist coated Si wafer, and selectively etching back the photoresist deposited outside and inside the trench; selectively etching the doped oxide layer to the photoresist remaining in the trench, together with the oxide layer; and completely removing the photoresist remaining inside the trench, and thermal processing the doped oxide inside the trench, thereby forming a selective doping region along the wall of the trench in the Si wafer.
Claim 3
Dependent Claim
70 words
The method for manufacturing a trench capacitor using a photoresist etch back process of claim 1 wherein the photoresist etch back process is a wet station-method which comprises dipping the Si wafer having the trench, on which photoresist is coated by dynamic double coating process, planarized and baked thereof, in the wet sink containing the mixture of water and developer, and selectively etching back the photoresist according to a target.
Claim 4
Dependent Claim
52 words
The method for manufacturing a trench capacitor using a photoresist etch back process of claim 2 wherein the photoresist etch back process by wet station-method further comprises determining etching time by calculating the desired etching thickness of photoresist, after first determining the photoresist etch rate outside the trench by sample etching thereof.
Claim 5
Dependent Claim
66 words
The method for manufacturing a trench capacitor using a photoresist etch back process of claim 1 wherein the photoresist etch back process includes a track method which comprises developing a Si wafer having the trench, on which a photoresist is coated by a dynamic double coating process, planarized and baked, with the developer on the track, and selectively etching back the photoresist according to a target.
Claim 6
Dependent Claim
38 words
The method for manufacturing trench capacitor using photoresist etch back process of claim 2 wherein the photoresist etch back process by the track-method comprises determining etching time by controlling etching speed according to the developer and baking temperature.
Claim 7
Dependent Claim
75 words
The method for manufacturing a trench capacitor using a photoresist etch back process of claim 1, wherein the photoresist etch back process includes as Oxygen plasma-gas method which comprises exposing the Si wafer, on which photoresist is coated by dynamic double coating process planarized and baked, to an Oxygen plasma gas with a dry etcher, and selectively etching back the photoresist by controlling the amount of the gas, voltage or pressure of the dry etcher.
Claim 8
Dependent Claim
51 words
The method for manufacturing a trench capacitor using a photoresist etch back process of claim 6 wherein the photoresist etch back process by Oxygen plasma-gas method comprises determining photoresist etch rate inside the trench by using SEM, detecting etch end point of Si wafer surface by using end point detector system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |