Power field effect devices having low gate sheet resistance and low ohmic contact resistance

Claim 1

A multi-cellular, field effect, power semiconductor device comprising: a body of semiconductor material having opposed first and second major surfaces and a first region of one type conductivity extending to said first major surface, said first major surface being planar; an insulated gate electrode layer disposed on said first major surface, said insulated gate electrode having a plurality of apertures therein; said gate electrode layer including: an oxide layer formed on said first major surface of said wafer, a polysilicon layer formed on said oxide layer, a tungsten silicide layer formed on said polysilicon layer, and said gate electrode's oxide layer, polysilicon layer and tungsten silicide layer having vertically aligned edge profiles; a plurality of cells, each associated with one of said apertures in said gate electrode layer, each of said cells comprising: a second region of opposite type conductivity extending into said first region from said first major surface beneath the gate electrode aperture for that cell, a third region of said one type conductivity disposed in said second region and extending to said first major surface, said second and third regions being self-aligned with respect to the gate electrode aperture for that cell, said second region including a channel portion disposed between said first and third regions, beneath said insulated gate electrode and self-aligned with respect to the gate electrode aperture for that cell, and said second and third regions having a layer of tungsten disposed thereon in ohmic contact therewith, said tungsten layer being self-aligned with respect to said aperture in said gate electrode and spaced from said gate electrode; a layer of dielectric disposed over said body of semiconductor material and having a plurality of contact apertures therein, each of said contact apertures being situated over said tungsten layer of a different cell, said dielectric layer being disposed between said tungsten layer and said insulated gate electrode layer; and a layer of metallization disposed over said dielectric layer, extending into said contact aperture and into ohmic contact with each of said tungsten layers.