Low loss fet

Claim 2

In a field effect transistor (FET) formed on a base member and having a doped semiconductive body region, a gate insulative layer overlying the body region, a gate member at least partially overlying the insulative layer, a gate connection on a gate member, a source connection laterally spaced from the gate insulative layer, a doped semiconductive extension of the source underlying a portion of the gate insulative layer and laterally contacting the body region, and a drain means contacting an opposed side of the body region from the source extension, the improvement comprising: said gate member comprising a layer of polysilicon capped by a conductive coating formed from a silicide of a refractory metal, said sources extension being laterally spaced from said source connection, and a conductive strip of substantially lower resistivity than either the source extension or the body area under the source extension, said conductive strip spanning the spacing between said source extension and said source connection and providing a low resistance path therebetween said conductive strip being formed from the same silicide material as said conductive coating on said gate member and having a thickness substantially equal to the thickness of said conductive coating.

Claim 3

The FET of claim 1, wherein the source extension is substantially restricted to the area underlying the gate insulative layer.

Claim 4

The FET of claim 2, wherein the conductive strip comprises a layer of conductive material underlying the source connection and extending generally laterally therefrom to a location contacting the gate insulative layer.

Claim 5

The FET of claim 1, implemented as a vertical device in which the drain means comprises a doped semiconductive material of opposite polarity to the body region extending through the base member to the opposite side thereof from the gate insulative layer.

Claim 6

A self-aligned, low loss field effect transistor (FET), comprising: a base member formed from a semiconductive material, a gate insulative layer formed on the base member, a gate member formed on one side of the gate insulative layer, said gate member comprising a layer of polysilicon capped by a conductive coating formed from a silicide of a refractory metal, a conductive strip extending along the base member substantially to the gate insulative layer at a location spaced from the gate member, said conductive strip being formed from the same silicide material as said conductive coating on said gate member and having a thickness substantially equal to the thickness of said conductive coating, a source electrode formed on the conductive layer and spaced from the gate insulative layer, a doped semiconductive extension of the source laterally spaced from the source electrode and extending from the conductive strip along the opposite side of the gate insulative layer from the gate member, a doped semiconductive channel region of opposite conductivity to the source extension extending from the source extension along the opposite side of the gate insulative layer from the gate member, and a drain means contacting an opposed side of the channel region from the source extension.

Claim 7

A self-aligned, low loss field effect transistor (FET), comprising: a base member formed from a semiconductive material, a gate insulative layer formed on the base member, a gate member formed on one side of the gate insulative layer, said gate member comprising a layer of polysilicon capped by a conductive coating formed from a silicide of a refractory metal, a conductive strip extending along the base member substantially to the gate insulative layer at a location spaced from the gate member, said conductive strip being formed from the same silicide material as said conductive coating on said gate member and having a thickness substantially equal to the thickness of said conductive coating, a source electrode formed on the conductive layer and spaced from the gate insulative layer, a doped semiconductive extension of the source laterally spaced from the source electrode and extending from the conductive strip along the opposite side of the gate insulative layer from the gate member, a doped semiconductive channel region of opposite conductivity to the source extension extending from the source extension along the opposite side of the gate insulative layer from the gate member, and a drain means contacting an opposed side of the channel region from the source extension.

Claim 8

The FET of claim 5, implemented as a vertical device in which the drain means comprises a doped semiconductive material of opposite polarity to the channel region extending through the base member to the opposite side thereof from the gate insulative layer.

Claim 9

The FET of claim 1, said conductive strip providing a short circuit between said source connection and said body region.

Claim 10

The FET of claim 5, said conductive strip providing a short circuit between said source and said base member.

Claim 11

The FET of claim 1, wherein said conductive coating and conductive strip are formed from platinum silicide.

Claim 12

The FET of claim 5, wherein said conductive coating and conductive strip are formed from platinum silicide.

Claim 13

The FET of claim 1, implemented as a lateral device in which the drain means comprises a doped semiconductive drain extension underlying a portion of the gate insulative layer and laterally contacting the body region at a location opposed to the source extension, a drain connection laterally spaced from the gate insulative layer, and a second conductive strip of substantially lower resistivity than the drain extension providing a low resistance path between the drain connection and the drain extension, said second conductive strip being formed from the same silicide material as said conductive coating on said gate member and having a thickness substantially equal to the thickness of said conductive coating.

Claim 14

The FET of claim 5, implemented as a lateral device in which the drain means comprises a second conductive strip extending along the base member and contacting the gate insulative layer at a location spaced from both the gate member and the channel region, a drain electrode formed on the second conductive layer, and a doped semiconductive extension of the drain extending from the second conductive strip to the channel region, said second conductive strip being formed from the same silicide material as said conductive coating on said gate member and having a thickness substantially equal to the thickness of said conductive coating.