Multiple insulating layer for two-level interconnected metallization in semiconductor integrated circuit structures

Claim 1

A method of making an integrated circuit structure based on a silicon body including the system of: (a) forming a first electrically conductive region overlying a top surface of the body; (b) forming a first insulating region of essentially silicon dioxide, containing a first concentration of phosphorus, overlying the first conductive region; (c) treating an upper surface of the first insulating region to form a substantially planar upper surface thereof; (d) depositing a second insulating region of essentially silicon dioxide and of substantially uniform thickness upon the substantially planar upper surface of the first insulating region, whereby at least a portion of an upper surface of the second insulating region is substantially planar, the first insulating region containing a concentration of phosphorus which is higher than that of the second insulating region; and (e) forming a second electrically conductive region upon a portion of the upper surface of the second insulating region.

Claim 2

A method of making an integrated circuit structure based on a silicon body including the system of: (a) forming a first electrically conductive region overlying a top surface of the body; (b) forming a first insulating region of essentially silicon dioxide, containing a first concentration of phosphorus, overlying the first conductive region; (c) treating an upper surface of the first insulating region to form a substantially planar upper surface thereof; (d) depositing a second insulating region of essentially silicon dioxide and of substantially uniform thickness upon the substantially planar upper surface of the first insulating region, whereby at least a portion of an upper surface of the second insulating region is substantially planar, the first insulating region containing a concentration of phosphorus which is higher than that of the second insulating region; and (e) forming a second electrically conductive region upon a portion of the upper surface of the second insulating region.

Claim 8

A method of making a semiconductor integrated circuit containing a plurality of transistors integrated in the body at a major surface thereof comprising the steps of: (a) forming a field oxide insulating layer overlying the major surface at areas thereof located between the transistors; (b) forming a first level metallization strip comprising aluminum overlying a first portion of the field oxide insulating layer; (c) forming a first insulating layer comprising silicon dioxide overlying both the first level metallization strip and at least a portion of the field insulating layer; (d) substantially planarizing a top surface of the first insulating layer; (e) forming a second insulating layer of substantially uniform thickness, comprising silicon dioxide, upon the first insulating layer, whereby the top surface of the second insulating layer is also substantially planar, the first insulating layer containing a concentration of phosphorus which is higher than that of the second insulating layer; and (f) forming a second level metallization strip, comprising aluminum, overlying the second insulating layer.

Claim 9

A method of making a semiconductor integrated circuit containing a plurality of transistors integrated in the body at a major surface thereof comprising the steps of: (a) forming a field oxide insulating layer overlying the major surface at areas thereof located between the transistors; (b) forming a first level metallization strip comprising aluminum overlying a first portion of the field oxide insulating layer; (c) forming a first insulating layer comprising silicon dioxide overlying both the first level metallization strip and at least a portion of the field insulating layer; (d) substantially planarizing a top surface of the first insulating layer; (e) forming a second insulating layer of substantially uniform thickness, comprising silicon dioxide, upon the first insulating layer, whereby the top surface of the second insulating layer is also substantially planar, the first insulating layer containing a concentration of phosphorus which is higher than that of the second insulating layer; and (f) forming a second level metallization strip, comprising aluminum, overlying the second insulating layer.