US4319260A
Expired / Lapsed
US
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Multilevel interconnect system for high density silicon gate field effect transistors
Assignee: Texas Instruments Inc
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Filing: 1979-09-05
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Granted: 1982-03-09
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Expires: 1999-09-05
Abstract
Abstract A metal oxide semiconductor device having at least one level of polycrystalline silicon interconnects and novel insulation layers for multilevel interconnects. In one embodiment a layer of arsenic doped glass replaces the conventional phosphorus doped glass insulation layer. In other embodiments a layer of arsenic doped glass upon an undoped layer of silicon dioxide provides the insulation layer. Slow diffusing source-drain impurities along with these insulation layers provide minimum lateral source-drain diffusion.
Inventors
- 👤 Al F. Tasch, Jr.
- 👤 Horng-Sen Fu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:16
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10B; H10B12/00; H10B12/30; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/65; H10P14/6502; H10P14/6506; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6923; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/47; H10W20/48
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
102 words
A semiconductor device comprising: a semiconductor body of P type conductivity; a pair of N type regions in said body and adjacent to the surface of said body, said regions being doped with slow diffusion impurity; an insulating layer upon said surface, disposed between and partially overlapping said regions; a conductive member upon said first layer partially overlapping said regions; and a multilevel interconnect system insulating layer of arsenic doped glass upon a layer of silicon dioxide upon said conductive member and said regions wherein said layer of silicon dioxide acts as a barrier to diffusion of arsenic from said arsenic glass.
Claim 2
Dependent Claim
102 words
A semiconductor device comprising: a semiconductor body of P type conductivity; a pair of N type regions in said body and adjacent to the surface of said body, said regions being doped with slow diffusion impurity; an insulating layer upon said surface, disposed between and partially overlapping said regions; a conductive member upon said first layer partially overlapping said regions; and a multilevel interconnect system insulating layer of arsenic doped glass upon a layer of silicon dioxide upon said conductive member and said regions wherein said layer of silicon dioxide acts as a barrier to diffusion of arsenic from said arsenic glass.
Claim 3
Dependent Claim
14 words
A device according to claim 1, wherein said conductive member is a polycrystalline silicon.
Claim 4
Dependent Claim
15 words
A device according to claim 1, wherein said pair of N type regions include arsenic.
Claim 5
Dependent Claim
15 words
A device according to claim 1, wherein said pair of N type regions include antimony.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-03-08 | 1985-09-07 | 1986-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-03-08 | 1989-09-07 | 1990-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-03-08 | 1993-09-07 | 1994-03-09 | $7700.00 | Window Closed / Lapsed |