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JPS577153A Expired / Lapsed JP ⏱️ 0.0 years remaining

Preparation of semiconductor device

Assignee: NEC Corp
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Filing: 1980-06-16
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Granted: —
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Expires: 2000-06-16
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Abstract

Abstract PURPOSE:To shorten the manufacture process by a method wherein, when impurities each conductive in the opposite direction are introduced into the channel regions of depletion D type and enhancement E type FET's, either one of them is introduced without the use of a photoresist mask. CONSTITUTION:A P<+> guard ring 5 and a field oxide film 6a are formed on a P type Si substrate 1, and a P layer 8 is then formed by injecting ions through a gate oxide film 6b. After this, an N layer 7 is formed by injecting phosphorus ions, using a photoresist mask 4a. An opening is made in the oxide film 6b, which is followed by the formation of an oxide film 6c after poly-Si 10 is laid on the surface. Then gates 11, 11a and a connecting layer 19 are formed by etching the layers 6c and 10. Next, an oxide film 6d is used to cover the surface and phosphorus diffusion is provided so as to place sources 12, 12a and drains 13, 13a. After the resistance of the gate and the connecting layer is reduced, both are oxidized to produce an oxide film 6e and PSG14 under the film 6e. An opening is selectively made and poly-Si 10a are laid, where phosphorus diffusion is again provided. Al wiring 15 is provided and the layer 10 is etched. Next the surface is covered with an oxide film 6f and the pad of the wiring 15 is opened to complete the device, so that the manufacturing process can be made in a shorter time than before.

Inventors

  • 👤 Katsuhiko Suzuki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 16:20
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/02; H10D84/03; H10D84/038

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