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US4980301A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for reducing mobile ion contamination in semiconductor integrated circuits

Assignee: Nokia Bell Labs
•
Filing: 1990-02-23
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Granted: 1990-12-25
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Expires: 2010-02-23
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Abstract

Abstract In a method of fabricating semiconductor integrated circuits, the effects of mobile ion contamination in a dielectric layer which has been subjected to a source of mobile ion contamination, e.g., reactive ion etching, is substantially eliminated by removing substantially only the topmost portion of the dielectric layer, e.g., 10-15 nm of an 800 nm layer, promptly after performing the step which produced the source of contamination.

Inventors

  • 👤 Alain S. Harrus
  • 👤 Graham W. Hills
  • 👤 Cris W. Lawrence
  • 👤 Morgan J. Thoma

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 19:08
CPC Classifications
H; H10; H10P; H10P95/00; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 86 words
A method of fabricating a semiconductor integrated circuit, including the step of planarizing a dielectric layer disposed over a silicon substrate, wherein said planarizing is accomplished by steps comprising dry anisotropic etching of said dielectric layer, characterized by the further step of wet etching only the topmost portions of the dielectric layer after the planarizing step, thereby to remove substantially all of the mobile ion contamination from the dielectric layer that is introduced by said planarizing step; and thereafter forming contact windows in said dielectric layer.
Claim 2
Independent Claim 86 words
A method of fabricating a semiconductor integrated circuit, including the step of planarizing a dielectric layer disposed over a silicon substrate, wherein said planarizing is accomplished by steps comprising dry anisotropic etching of said dielectric layer, characterized by the further step of wet etching only the topmost portions of the dielectric layer after the planarizing step, thereby to remove substantially all of the mobile ion contamination from the dielectric layer that is introduced by said planarizing step; and thereafter forming contact windows in said dielectric layer.
Claim 3
Dependent Claim 12 words
The method of claim 1 wherein the wet etching employs hydrofluoric acid.
Claim 4
Dependent Claim 28 words
The method of claim 1 wherein the dielectric layer is of thickness greater than about 600 nm and the topmost portion removed is less than about 100 nm.
Claim 5
Dependent Claim 14 words
The method of claim 1 wherein said dry anisotropic etching is reactive ion etching.
Claim 6
Dependent Claim 31 words
The method of claim 1 wherein said dielectric layer is a deposited second dielectric layer disposed over a first dielectric layer on which is disposed a first level of metal interconnection.
Claim 7
Dependent Claim 12 words
The method of claim 5 wherein the second dielectric layer is PETEOS.

References Cited (Backward Citations)

US4102733A Cited
JPS5683977A Cited
US4361599A Cited
US4520554A Cited
JPS60193324A Cited
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US4795722A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-12-24 1994-06-25 1994-12-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-12-24 1998-06-25 1998-12-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-12-24 2002-06-25 2002-12-25 $7700.00 Window Closed / Lapsed

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