Static random access memory device with voltage control circuit

Claim 2

A static random access memory device comprising: a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells each coupled to corresponding ones of said word lines and between each of corresponding ones of said pairs of bit lines, a plurality of N-channel MOS transistors having drain and gate electrodes each coupled together, being connected between a first node and a second node; a N-channel MOS transistor having a drain-source path coupled between said second node and a reference voltage node, and having a gate coupled to said first node; a resistance coupled between said first node and a third node; a third N-channel MOS transistor having a gate coupled to said second node and a drain-source path coupled between said third node and the reference voltage node; inverting means coupled between said third node and the gate of P-channel MOS transistors for providing an output signal indicating a relation between an external power supply voltage and a voltage level; and means for supplying selectively one of an external power supply voltage and a voltage lower than the external power supply voltage, to each of said memory cells, in response to the output signal.

Claim 3

The static random access memory device of claim 1, wherein said supplying means comprises a P-channel MOS transistor and a N-channel MOS transistor having drain-source paths each coupled in parallel between a first node and a common power supply line, a gate of said N-channel MOS transistor being coupled to said first node.

Claim 4

The static random access memory device of claim 2, wherein substrate of said P-channel MOS transistor is coupled to said first node, and substrate of said N-channel MOS transistor is coupled to reference voltage node.

Claim 5

A static random access memory device, comprising: a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells each coupled to corresponding ones of said word lines and between each of corresponding ones of said paris of bit lines; power supply voltage regulating means coupled to each said memory cell, for decreasing a supply voltage delivered to each said memory cell when a voltage of an external power supply exceeds a specified voltage level, and for applying the external power supply to each said memory cell when the external power supply voltage does not exceed the specified voltage level; said power supply voltage regulating means comprising: first means for detecting and providing an output signal indicating whether the voltage of the external power supply exceeds the specified voltage level, and second means for supplying selectively one of the external power supply voltage and a voltage lower than the external power supply voltage, to said each memory cell, in response to the output signal of said first means; said first means comprising: a plurality of N-channel MOS transistors having drain and gate electrodes each coupled together, coupled between said first node and a second node, a N-channel MOS transistor having a drain-source path coupled between said second node and the reference voltage node, and a having gate coupled to said first node, a resistance coupled between said first node and a third node, a third N-channel MOS transistor having a gate coupled to said second node and a drain-source path coupled between said third node and the reference voltage node, and inverter means coupled between said third node and an output node, for providing said output signal.

Claim 6

A static random access memory device, comprising: a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells each coupled to corresponding ones of said word lines and between each of corresponding ones of said paris of bit lines; power supply voltage regulating means coupled to each said memory cell, for decreasing a supply voltage delivered to each said memory cell when a voltage of an external power supply exceeds a specified voltage level, and for applying the external power supply to each said memory cell when the external power supply voltage does not exceed the specified voltage level; said power supply voltage regulating means comprising: first means for detecting and providing an output signal indicating whether the voltage of the external power supply exceeds the specified voltage level, and second means for supplying selectively one of the external power supply voltage and a voltage lower than the external power supply voltage, to said each memory cell, in response to the output signal of said first means; said first means comprising: a plurality of N-channel MOS transistors having drain and gate electrodes each coupled together, coupled between said first node and a second node, a N-channel MOS transistor having a drain-source path coupled between said second node and the reference voltage node, and a having gate coupled to said first node, a resistance coupled between said first node and a third node, a third N-channel MOS transistor having a gate coupled to said second node and a drain-source path coupled between said third node and the reference voltage node, and inverter means coupled between said third node and an output node, for providing said output signal.

Claim 7

The static random access memory device of claim 4, wherein said resistor is formed from a polycrstalline silicon of high resistance.

Claim 8

The static random access memory device of claim 4, wherein said resistor is formed from a polycrstalline silicon of high resistance.

Claim 9

A static random access memory device, comprising: a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells coupled between said word lines and pairs of bit lines; a plurality of first ones of a first-conductivity-type channel MOS transistors having drain and gate electrodes each coupled together with said plurality of first transistors coupled between a first node and a second node; a second one of said first conductivity-type channel MOS transistor having a drain-source path coupled between said second node and the reference voltage node, and having a gate coupled to said first node; an impedance coupled between said first node and a third node; a third one of said first conductivity-type MOS transistor having a gate coupled to said second node and a drain-source path coupled between said third node and a reference voltage node; inverter means coupled between said third node and an output node, for providing an output signal at said output node indicative of a relation between a power supply and a reference potential; and means for supplying selectively one of the power supply voltage and a voltage lower than the power supply voltage, to said each of said memory cells, in response to the output signal.

Claim 10

A static random access memory device, comprising: a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells coupled between said word lines and pairs of bit lines; a plurality of first ones of a first-conductivity-type channel MOS transistors having drain and gate electrodes each coupled together with said plurality of first transistors coupled between a first node and a second node; a second one of said first conductivity-type channel MOS transistor having a drain-source path coupled between said second node and the reference voltage node, and having a gate coupled to said first node; an impedance coupled between said first node and a third node; a third one of said first conductivity-type MOS transistor having a gate coupled to said second node and a drain-source path coupled between said third node and a reference voltage node; inverter means coupled between said third node and an output node, for providing an output signal at said output node indicative of a relation between a power supply and a reference potential; and means for supplying selectively one of the power supply voltage and a voltage lower than the power supply voltage, to said each of said memory cells, in response to the output signal.

Claim 11

The static random access memory device of claim 7, wherein said inverter means comprises a P-channel MOS transistor and a N-channel MOS transistor having drain-source paths are coupled in parallel between a first node and a common power supply line, a gate of said N-channel MOS transistor being coupled to said first node.

Claim 12

The static random access memory device of claim 8, wherein substrate of said P-channel MOS transistor is coupled to said first node, and substrate of said N-channel MOS transistor is coupled to reference voltage node.

Claim 13

The static random access memory device of claim 9, wherein said impedance is formed from a polycrystalline silicon layer exhibiting a high resistance.

Claim 14

A random access memory device, having a plurality of memory cells, comprising: a plurality of first of a first-conductivity-type transistors having drain and gate electrodes each coupled together, coupled between a first node and a second node; a second first-conductivity-type transistor having a drain-source path coupled between said second node and a reference node, and a having gate coupled to said first node; an impedance coupled between said first node and a third node; a third first-conductivity-type channel transistor having a gate coupled to said second node and a drain-source path coupled between said third node and the reference node, and inverter means coupled between said third node and an output node, for providing an output signal indicating a relation between a first supply voltage and a reference voltage; and means for supplying to said plurality of memory cells, one of said first supply voltage and a second supply voltage having an amplitude different than said first supply voltage, in response to said output signal.

Claim 15

A random access memory device, having a plurality of memory cells, comprising: a plurality of first of a first-conductivity-type transistors having drain and gate electrodes each coupled together, coupled between a first node and a second node; a second first-conductivity-type transistor having a drain-source path coupled between said second node and a reference node, and a having gate coupled to said first node; an impedance coupled between said first node and a third node; a third first-conductivity-type channel transistor having a gate coupled to said second node and a drain-source path coupled between said third node and the reference node, and inverter means coupled between said third node and an output node, for providing an output signal indicating a relation between a first supply voltage and a reference voltage; and means for supplying to said plurality of memory cells, one of said first supply voltage and a second supply voltage having an amplitude different than said first supply voltage, in response to said output signal.

Claim 16

The random access memory device of claim 11, wherein said inverter means comprises: a first of a second-conductivity-type channel transistor having a source-drain path coupled between said first node and output node, and a gate coupled to said third node; and a fourth first conductivity-type channel transistor having a source-drain path coupled between said output node and reference node.

Claim 17

The random access memory device of claim 12 further comprises of a first of a substrate of said first second-conductivity-type channel transistor is coupled to said first node, and substrate of said fourth first-conductivity-type channel transistor is coupled to said reference node.

Claim 18

The random access memory device of claim 12, wherein said supplying means comprises: a second second-conductivity-type channel transistor having a gate coupled to said output node; a fifth first-conductivity-type channel transistor; said first second-conductivity-type channel transistor and fourth first-conductivity-type channel transistor having drain-source paths being coupled in parallel between said first node and said plurality of memory cells.

Claim 19

The random access memory device of claim 11, wherein said supplying means comprises: a first of a second-conductivity-type channel transistor having a gate coupled to said output node; a fourth first-conductivity-type channel transistor; said first second-conductivity-type channel transistor and fourth first-conductivity-type channel transistor having drain-source paths being coupled in parallel between said first node and said plurality of memory cells.

Claim 20

The random access memory device of claim 15, further comprised of a substrate first of said second-conductivity-type channel transistor is coupled to said first node, and substrate fourth of said first-conductivity-type channel transistor is coupled to said reference node.