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US4948993A
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Distributed sensing control circuit for a sense amplifier of the memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1988-12-27
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Granted: 1990-08-14
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Expires: 2008-12-27
Abstract
Abstract A distributed control circuit for a sense amplifier is provided in which each sense amplifier has a pair of sensing control transistors connected in serial with each sensing node of the sense amplifiers. Each gate of the sensing control transistors has a respective resistor connected in sequence from the gate of the uppermost sensing control transistor to the gate of the lowermost sensing transistor. A delay compensation resistor is connected by the unit of a sensing control transistor group having the number of the sensing control transistors as many as an integer k.
Inventors
- 👤 Dae-Je Chin
- 👤 Chang-Hyun Kim
- 👤 Hong-Sun Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
269 words
A distributed sensing control circuit for a sense amplifier of a memory device comprising: (a) a plurality of first sensing control transistors for controlling a plurality of sense amplifiers each having a pair of sensing nodes, each of said first sensing control transistors being connected to one of the sensing nodes of a corresponding one of said sense amplifiers, said one sensing nodes of said amplifiers being connected in common to a recharge circuit; (b) a plurality of second sensing control transistors for controlling the plurality of sense amplifiers, each of said second sensing control transistors being connected to one of the other sensing nodes of a corresponding one of said sense amplifiers, said other sensing nodes being connected in common to said recharge circuit; (c) first and second power terminals for the application therebetween of a source of power, each of said first and second control transistors and said sense amplifiers being connected between said power terminals; and (d) a plurality of resistor means connected one by one to each of gates of said sensing control transistors, said resistor means being connected in sequence through each of the gates of said first and second sensing control transistors, respectively, thereby arraying each of said first and second control transistors in respective first and second sequences of transistors, whereby the turn-on time of each of the sensing control transistors in each sequence is delayed in sequential order after a sensing control signal is applied to the gate of the sensing control transistor first in line in each sequence because the applied sensing control signal is delayed by said resistor means.
Claim 2
Dependent Claim
269 words
A distributed sensing control circuit for a sense amplifier of a memory device comprising: (a) a plurality of first sensing control transistors for controlling a plurality of sense amplifiers each having a pair of sensing nodes, each of said first sensing control transistors being connected to one of the sensing nodes of a corresponding one of said sense amplifiers, said one sensing nodes of said amplifiers being connected in common to a recharge circuit; (b) a plurality of second sensing control transistors for controlling the plurality of sense amplifiers, each of said second sensing control transistors being connected to one of the other sensing nodes of a corresponding one of said sense amplifiers, said other sensing nodes being connected in common to said recharge circuit; (c) first and second power terminals for the application therebetween of a source of power, each of said first and second control transistors and said sense amplifiers being connected between said power terminals; and (d) a plurality of resistor means connected one by one to each of gates of said sensing control transistors, said resistor means being connected in sequence through each of the gates of said first and second sensing control transistors, respectively, thereby arraying each of said first and second control transistors in respective first and second sequences of transistors, whereby the turn-on time of each of the sensing control transistors in each sequence is delayed in sequential order after a sensing control signal is applied to the gate of the sensing control transistor first in line in each sequence because the applied sensing control signal is delayed by said resistor means.
Claim 3
Dependent Claim
242 words
A distributed sensing control circuit for a sense amplifier of a memory device comprising: (a) a plurality of first sensing control transistors for controlling a plurality of sense amplifiers each having a pair of sensing nodes, each of said first sensing control transistors being connected to one of the sensing nodes of a corresponding one of said sensing amplifiers; (b) a plurality of second sensing control transistors for controlling the plurality of sense amplifiers, each of said second sensing control transistors being connected to one of the other sensing nodes of a corresponding one of said sensing amplifiers; (c) first and second power terminals for the application therebetween of a source of power, each of said first and second control transistors and said sense amplifiers being connected between said power terminals; and (d) a plurality of resistor means connected one by one to each of gates of said sensing control transistors, said resistor means being connected in sequence through each of the gates of said first and second sensing control transistors, respectively, thereby arraying each of said first and second control transistors in respective first and second sequences of transistors, whereby the turn-on time of each of the sensing control transistors in each sequence is delayed in sequential order after a sensing control signal is applied to the gate of the sensing control transistor first in line in each sequence because the applied sensing control signal is delayed by said resistor means.
Claim 4
Dependent Claim
242 words
A distributed sensing control circuit for a sense amplifier of a memory device comprising: (a) a plurality of first sensing control transistors for controlling a plurality of sense amplifiers each having a pair of sensing nodes, each of said first sensing control transistors being connected to one of the sensing nodes of a corresponding one of said sensing amplifiers; (b) a plurality of second sensing control transistors for controlling the plurality of sense amplifiers, each of said second sensing control transistors being connected to one of the other sensing nodes of a corresponding one of said sensing amplifiers; (c) first and second power terminals for the application therebetween of a source of power, each of said first and second control transistors and said sense amplifiers being connected between said power terminals; and (d) a plurality of resistor means connected one by one to each of gates of said sensing control transistors, said resistor means being connected in sequence through each of the gates of said first and second sensing control transistors, respectively, thereby arraying each of said first and second control transistors in respective first and second sequences of transistors, whereby the turn-on time of each of the sensing control transistors in each sequence is delayed in sequential order after a sensing control signal is applied to the gate of the sensing control transistor first in line in each sequence because the applied sensing control signal is delayed by said resistor means.
Claim 5
Dependent Claim
90 words
A circuit according to claim 1 wherein consecutive ones of said control transistors of each of said sequences comprise groups of transistors each starting with a first one of said transistors, a pair of series connected resistance elements each extending in parallel with one of said sequences of control transistors, and means connecting each node between said resistance elements along each of said pair of series connected resistance elements with the gate of a different one of said first one of said transistors of each of said groups of transistors.
Claim 6
Dependent Claim
31 words
A distributed sensing control circuit for a sense amplifier of a memory device as claimed in claim 3, wherein each of said series connected resistance elements comprises a thin aluminum line.
Claim 7
Dependent Claim
90 words
A circuit according to claim 2 wherein consecutive ones of said control transistors of each of said sequences comprises groups of transistors each starting with a first one of said transistors, a pair of series connected resistance elements each extending in parallel with one of said sequences of control transistors, and means connecting each node between said resistance elements along each of said pair of series connected resistance elements with the gate of a different one of said first one of said transistors of each of said groups of transistors.
Claim 8
Dependent Claim
31 words
A distributed sensing control circuit for a sense amplifier of a memory device as claimed in claim 5, wherein each of said series connected resistance elements comprises a thin aluminum line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |