High performance dynamic sense amplifier with dual channel grounding transistor

Claim 1

A sense amplifier for a semiconductor memory device of the type having an array of rows and columns of memory cells with each column split into two column line halves and sense amplifiers connected to pairs of sense nodes at ends of each pair of column line halves, comprising: a pair of cross-coupled driver transistors, and first and second grounding transistors, each of the transistors being insulated-gate field effect transistors having a source-to-drain current path and a control gate electrode, means connecting the current path of each of the driver transistors separately between one of the sense nodes and a grounding node and connecting the current paths of both of the grounding transistors in parallel between the grounding node and reference potential, means for precharging the sense nodes to a voltage level prior to an active operating cycle, means for addressing a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, means for applying a first clock voltage to turn on the first grounding transistor at a first time subsequent to the said given time in the beginning of an active operating cycle and for applying a second clock voltage to turn on the second grounding transistor at a second time subsequent to the first time, said first grounding transistor being much smaller than the second grounding transistor, said second grounding transistor having a dual channel as the current path, and having a common control electrode for the dual channel with the second clock voltage being applied to such common control electrode, one part of the dual channel being implanted at an impurity doping level different from the other part, said one part thereby turning on prior to the other part of the channel.