Semiconductor sense circuit suitable for buffer circuit in semiconductor memory chip

Claim 2

A semiconductor sense circuit comprising: a reference voltage generating circuit for providing a reference voltage of a predetermined level; a sense amplifier, having first and second nodes, for amplifying a potential difference between signal voltages latched in said first and second nodes; first and second transfer gates for transferring an input signal and a reference voltage from said reference voltage generating circuit to first and second nodes of said sense amplifier, respectively, so that the input signal and the reference voltage are latched in said first and second nodes of said sense amplifier, respectively; and a level-shift circuit connected between said second node of said sense amplifier and said second transfer gate, and responsive to a voltage level of the input signal latched in said first node of said sense amplifier, for shifting the level of the reference voltage latched in said second node of said sense amplifier, said level-shift circuit shifting the level of the reference voltage latched in said second node of said sense amplifier to a level lower than the predetermined level when the input signal latched in said first node of said sense amplifier is high in voltage level, and to a level higher than the predetermined level when the input signal latched in said first node is low in voltage level.

Claim 3

The sense circuit according to claim 1, further comprising: means for supplying control signals to said first and second transfer gates and said level-shift circuit, so that the input signal and the reference voltage are latched in said first and second nodes of said sense amplifier, respectively, when said first and second transfer gates are turned off, and said level-shift circuit shifts the level of the reference voltage latched in said second node when said first and second transfer gates are turned off.

Claim 4

The sense circuit according to claim 1, wherein said level-shift circuit is formed of complementary MOS transistors.

Claim 5

The sense circuit according to claim 1, wherein said level-shift circuit is formed of N-channel MOS transistors.

Claim 6

The sense circuit according to claim 1, wherein said level-shift circuit comprises first and second P-channel MOS transistors, and third and fourth N-channel MOS transistors, drain-to-source paths of said first, second, third, and fourth transistors being series-connected, in this order, across a power source, a connection point of said second and third transistors being connected to said second node of said sense amplifier, and gates of said second and third transistors being connected together to said first node of said sense amplifier, and further comprising: means for applying control signals to said first and second transfer gates and gates of said first and fourth transistors, so that said first and fourth transistors are turned on when said first and second transfer gates are turned off.

Claim 7

The sense amplifier according to claim 1, wherein said level-shift circuit comprises first to sixth N-channel MOS transistors, drain-to-source paths of said first to fourth transistors being series-connected, in this order, across a power source, drain-to-source paths of said fifth and sixth transistors being series-connected across the power source, a connection point of said second and third transistors being connected to said second node of said sense amplifier, a connection point of said fifth and sixth transistors being connected to a gate of said second transistor, and gates of said third and sixth transistors being connected together to said first node of said sense amplifier, and further comprising: means for supplying control signals to said first and second transfer gates and gates of said first, fourth, and fifth transistors, so that said first, fourth, and fifth transistors are turned on when said first and second transfer gates are turned off.

Claim 8

An address buffer circuit for sensing an address signal addressing a semiconductor memory, the address signal consisting of a plurality of bits, comprising: a plurality of sense circuits formed in a semiconductor memory chip, for sensing the respective bits of an externally applied address signal; and a common reference voltage generating circuit formed in said semiconductor memory chip, for providing a reference voltage of a predetermined level; each of said plurality of sense circuits comprising: a sense amplifier, having a first and a second node, for amplifying a potential difference between signal voltages latched in said first and second nodes; first and second transfer gates for transferring an input signal for a corresponding bit of the address signal and the reference voltage from said reference voltage generating circuit to said first and second nodes of said sense amplifier, respectively, so that the input signal and the reference voltage are latched in said first and second nodes of said sense amplifier, respectively; and a level-shift circuit connected between said second node of said sense amplifier and said second transfer gate, and responsive to a voltage level of the input signal latched in said first node of said sense amplifier, for shifting the level of the reference voltage latched in said second node of said sense amplifier, said level-shift circuit shifting the level of the reference voltage latched in said second node of said sense amplifier to a level lower than the predetermined level of the reference voltage when the input signal latched in said first node of said sense amplifier is high in voltage level, and shifting the level of the reference voltage latched in said second node to a level higher than the predetermined level of the reference voltage when the input signal latched in said first node is low in voltage level.

Claim 9

An address buffer circuit for sensing an address signal addressing a semiconductor memory, the address signal consisting of a plurality of bits, comprising: a plurality of sense circuits formed in a semiconductor memory chip, for sensing the respective bits of an externally applied address signal; and a common reference voltage generating circuit formed in said semiconductor memory chip, for providing a reference voltage of a predetermined level; each of said plurality of sense circuits comprising: a sense amplifier, having a first and a second node, for amplifying a potential difference between signal voltages latched in said first and second nodes; first and second transfer gates for transferring an input signal for a corresponding bit of the address signal and the reference voltage from said reference voltage generating circuit to said first and second nodes of said sense amplifier, respectively, so that the input signal and the reference voltage are latched in said first and second nodes of said sense amplifier, respectively; and a level-shift circuit connected between said second node of said sense amplifier and said second transfer gate, and responsive to a voltage level of the input signal latched in said first node of said sense amplifier, for shifting the level of the reference voltage latched in said second node of said sense amplifier, said level-shift circuit shifting the level of the reference voltage latched in said second node of said sense amplifier to a level lower than the predetermined level of the reference voltage when the input signal latched in said first node of said sense amplifier is high in voltage level, and shifting the level of the reference voltage latched in said second node to a level higher than the predetermined level of the reference voltage when the input signal latched in said first node is low in voltage level.

Claim 10

A semiconductor sense circuit comprising; a reference voltage generating circuit for providing a reference voltage of a predetermined level; a sense amplifier, having a first and a second node, for amplifying a potential difference between signal voltages latched in said first and second nodes; first and second transfer gates for transferring an input signal and the reference voltage to said first and second nodes of said sense amplifier, respectively, so that the input signal and the reference voltage are latched in said first and second nodes of said sense amplifier, respectively; and a level-shift circuit connected between said second node of said sense amplifier and said second transfer gate, and responsive to a voltage level of the input signal latched in said first node of said sense amplifier, for shifting the level of the reference voltage latched in said second node of said sense amplifier.

Claim 11

A semiconductor sense circuit comprising; a reference voltage generating circuit for providing a reference voltage of a predetermined level; a sense amplifier, having a first and a second node, for amplifying a potential difference between signal voltages latched in said first and second nodes; first and second transfer gates for transferring an input signal and the reference voltage to said first and second nodes of said sense amplifier, respectively, so that the input signal and the reference voltage are latched in said first and second nodes of said sense amplifier, respectively; and a level-shift circuit connected between said second node of said sense amplifier and said second transfer gate, and responsive to a voltage level of the input signal latched in said first node of said sense amplifier, for shifting the level of the reference voltage latched in said second node of said sense amplifier.