Patent US4936950A successfully refreshed from Google Patents.
US4936950A
Expired / Lapsed
US
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Method of forming a configuration of interconnections on a semiconductor device having a high integration density
Assignee: US Philips Corp
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Filing: 1989-04-14
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Granted: 1990-06-26
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Expires: 2009-04-14
Abstract
Abstract A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the isolating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.
Inventors
- 👤 Trung T. Doan
- 👤 Leendert De Bruin
- 👤 Malcolm K. Grief
- 👤 Harald Godon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:45
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/032; H10W20/033
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
179 words
A method of manufacturing a configuration of interconnections on a semiconductor device, said method comprising: (a) forming an insulating layer on a substrate, provided with said semiconductor device, (b) providing said insulating layer with a separation layer capable of being etched selectively as to form openings corresponding to contact openings to be etched into said insulating layer, (c) selectively etching said openings corresponding to said contact openings into said separation layer, (d) etching said narrow contact openings into said insulating layer, (e) depositing at least one layer of conductive material, having an overall thickness which is sufficient to fill the volume of said contact openings, on said separation layer, (f) selectively removing, by etching the major part of said conductive material and said underlying separation layer to thereby expose the surface of said insulating layer while maintaining said conductive layer and said operation layer in said contact openings, (g) selectively removing said separation layer from said contact openings, and (h) depositing a metal interconnection layer on said insulating layer and etching said metallic interconnection layer into a desired configuration.
Claim 2
Independent Claim
179 words
A method of manufacturing a configuration of interconnections on a semiconductor device, said method comprising: (a) forming an insulating layer on a substrate, provided with said semiconductor device, (b) providing said insulating layer with a separation layer capable of being etched selectively as to form openings corresponding to contact openings to be etched into said insulating layer, (c) selectively etching said openings corresponding to said contact openings into said separation layer, (d) etching said narrow contact openings into said insulating layer, (e) depositing at least one layer of conductive material, having an overall thickness which is sufficient to fill the volume of said contact openings, on said separation layer, (f) selectively removing, by etching the major part of said conductive material and said underlying separation layer to thereby expose the surface of said insulating layer while maintaining said conductive layer and said operation layer in said contact openings, (g) selectively removing said separation layer from said contact openings, and (h) depositing a metal interconnection layer on said insulating layer and etching said metallic interconnection layer into a desired configuration.
Claim 3
Dependent Claim
29 words
A method as claimed in claim 1, characterized in that the separation layer is chosen so that it can be eliminated selectively with respect to the conductive filling material.
Claim 4
Dependent Claim
42 words
A method as claimed in claim 2, characterized in that the insulating layer is formed from a silica glass, the conductive filling material is formed from tungsten or an alloy rich in tungsten and the separation layer is formed from silicon nitride.
Claim 5
Dependent Claim
76 words
A method as claimed in claim 2, wherein the separation layer is chosen of the materials such that the conductive filling material can be etched selectively with respect to the separation layer and the separation layer is employed as an etch-stopping layer in the step in the method wherein the major part of the conductive material is etched to expose the surface of the insulating layer while the conductive material is maintained in the contact openings.
Claim 6
Dependent Claim
32 words
The method of claim 4, wherein during the step of etching the contact openings the separation layer is etched selectively and is used as an additional mask for etching said insulating layer.
Claim 7
Dependent Claim
39 words
A method as claimed in claim 5, characterized in that, the conductive filling material is formed from tungsten or an alloy rich in tungsten and the separation layer is formed from one of the metals: aluminum alloy or cobalt.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |