Frequency divider circuit with integer and non-integer divisors

Claim 2

A divide circuit for dividing an input signal having a predetermined frequency by either an integer or noninteger divisor to provide an output signal of divided frequency, said divide circuit comprising: counting means responsive to said input signal, for counting from a predetermined initial state value to a final predetermined state value at a rate determined by said input signal and generating a set of encoded output signals indicating a present state value of said counting means; first logic means coupled to the counting means and responsive to said set of output signals, said first logic means implementing a predetermined logical mapping of said output signals to provide a decoded output signal; and second logic means coupled to the first logic means further comprising: a first flip-flop responsive to said decoded output signal of said first logic means, said first flip-flop latching the decoded output signal from said first logic means at a rate determined by said input signal, and generating an output signal having a logic value determined by both the input signal and the decoded output signal; a second flip-flop also responsive to said decoded output signal of said first logic means and also latching the decoded output signal from said first logic means at a rate determined by said input signal, and generating an output signal having a logic value determined by both the input signal and the decoded output signal; and selection means responsive to said output signal of both said first and second flip-flops, said selection means dynamically selecting either said output signal of said first or said second flip-flop, in a sequence determined by the divisor, as the output signal of divided frequency.

Claim 3

The divide circuit of claim 1 wherein said second flip-flop of said second logic means latches data from said decoded output signal of said first logic means at a rate determined by said input signal with a predetermined frequency, but delayed by substantially one-half cycle of said input signal.

Claim 4

The divide circuit of claim 2 wherein said counting means is a polynomial counter which counts from a first state value to a second state value based on a predetermined logical combination of the encoded output signals.

Claim 5

A divide circuit for dividing an input signal having a predetermined frequency, said divide circuit comprising: counting means responsive to said input signal for counting, in either a first counting sequence, from an first initial state value to a first final state value at a rate determined by said input signal, or in a second counting sequence, from a second initial state value to a second final state value at a rate determined by said input signal, said counting sequence determined by a select signal, said counting means generating a set of encoded output signals indicating a present state value of said counting means; first logic means responsive to said encoded output signals, said first logic means implementing either a first or a second predetermined logical mapping of said encoded output signals in response to the select signal to provide a decoded output signal; and p1 second logic means coupled to the first logic means, comprising: a first flip-flop responsive to said decoded output signal, said first flip-flop latching the decoded output signal on a clock edge of first transitioning direction of the input signal, and generating an output signal in response thereto; a second flip-flop also responsive to said decoded output signal, said second flip-flop latching the decoded output signal on a clock edge of second transitioning direction of the input signal, and generating an output signal in response thereto; a third flip-flop coupled to the first flip-flop and being responsive to said output signal of said first flip-flop and generating an output signal in response thereto; and a multiplexor with a first input coupled to said output signal of said first flip-flop, a second input coupled to said output signal of said second flip-flop, and a third input coupled to said output signal of said third flip-flop, said third flip-flop controlling selection by the multiplexor of one of the outputs of the first and second flip-flops to provide as a divided frequency output signal.

Claim 6

A divide circuit for dividing an input signal having a predetermined frequency, said divide circuit comprising: counting means responsive to said input signal for counting, in either a first counting sequence, from an first initial state value to a first final state value at a rate determined by said input signal, or in a second counting sequence, from a second initial state value to a second final state value at a rate determined by said input signal, said counting sequence determined by a select signal, said counting means generating a set of encoded output signals indicating a present state value of said counting means; first logic means responsive to said encoded output signals, said first logic means implementing either a first or a second predetermined logical mapping of said encoded output signals in response to the select signal to provide a decoded output signal; and p1 second logic means coupled to the first logic means, comprising: a first flip-flop responsive to said decoded output signal, said first flip-flop latching the decoded output signal on a clock edge of first transitioning direction of the input signal, and generating an output signal in response thereto; a second flip-flop also responsive to said decoded output signal, said second flip-flop latching the decoded output signal on a clock edge of second transitioning direction of the input signal, and generating an output signal in response thereto; a third flip-flop coupled to the first flip-flop and being responsive to said output signal of said first flip-flop and generating an output signal in response thereto; and a multiplexor with a first input coupled to said output signal of said first flip-flop, a second input coupled to said output signal of said second flip-flop, and a third input coupled to said output signal of said third flip-flop, said third flip-flop controlling selection by the multiplexor of one of the outputs of the first and second flip-flops to provide as a divided frequency output signal.

Claim 7

The divide circuit of claim 4 wherein said counting means is a polynomial counter which counts from a first state value to a second state value based on a predetermined logical combination of the encoded output signals.

Claim 8

The divide circuit of claim 5 wherein said counting means further comprises: means for resetting said counting means to either the first initial state value of said first counting sequence or to the second initial state value of said second counting sequence in response to a reset signal.

Claim 11

The method of claim 7 wherein the step of generating encoded output signals further comprises the step of: sequentially providing state values as the encoded output signals in response to the encoded output signals, each state value provided in response to a predetermined logical combination of the encoded output signals.

Claim 12

The method of claim 8 wherein the step of latching the decoded signal in the second flip-flop further comprises the step of: delaying said latching in the second flip-flop substantially by one-half of a cycle of said input signal.

Claim 13

The method of claim 9 further comprising the step of: resetting said digital counter to said initial logic value in response to a reset signal.

Claim 16

The method of claim 11 wherein the step of generating a set of encoded output signals further comprises the step of: sequentially providing state values as the encoded output signals in response to the encoded output signals, each state value provided in response to a predetermined logical combination of the encoded output signals.

Claim 17

The method of claim 11 wherein the step of latching the decoded signal in the second flip-flop further comprises the step of: delaying said latching in the second flip-flop substantially by one-half of a cycle of said input signal.

Claim 18

The method of claim 13 further comprising the step of: resetting the counting of state values in response to a reset signal.