Logic coincidence gate, triplet of logic gates and sequential logic circuit using this logic gate

Claim 2

A coincidence logic gate comprising: two parallel-mounted inverters wherein each inverter comprises, a transistor having its source grounded; a saturable resistor coupled to the drain of said transistor; a means for supplying--a voltage to said transistor's drain through said saturable resistor; means for inputting a signal to a gate electrode of the transistor in said first inverter; means for inputting a clock signal to a gate electrode of the transistor in said second inverter; a third transistor having its source connected to the saturable resistor associated with said second transistor, in said second inverter, and wherein the drain and gate electrode of said third transistor are connected between the saturable resistor of the first inverter and the transistor of the first inverter; and wherein the first inverter has at least one signal input and the output of said entire logic gate is taken at a common point between said saturable resistor associated with said second inverter and said third transistor.

Claim 3

A logic gate according to the claim 1 wherein the first inverter comprises at least one additional input at the source of a fourth transistor which is connected in parallel to the first transistor and forms an OR function.

Claim 4

A triplet of logic gates comprising: three gates wherein each gate comprises: two parallel-mounted inverters wherein each inverter comprises: a transistor having its source grounded; a saturable resistor coupled to the drain of said transistor; means for supplying a voltage to said transistor's drain through said saturable resistor; means for inputting a signal to a gate electrode of the transistor in said first inverter; means for inputting a clock signal to an electrode of the transistor in said second inverter; a third transistor having its source connected to the saturable resistor associated with said second transistor, in said second inverter, and wherein the drain and gate electrode of said third transistor are connected between the saturable resistor of the first inverter and the transistor of the first inverter; and wherein the first inverter has at least one signal input and the output of said entire logic gate is taken at a common point between said saturable resistor associated with said second inverter and said third transistor; wherein the input of said triplet is in the input of said first gate, the output is the output of said second gate and wherein said third gate has an additional input means and wherein the output of said third gate is re-looped.

Claim 5

A triplet of logic gates comprising: three gates wherein each gate comprises: two parallel-mounted inverters wherein each inverter comprises: a transistor having its source grounded; a saturable resistor coupled to the drain of said transistor; means for supplying a voltage to said transistor's drain through said saturable resistor; means for inputting a signal to a gate electrode of the transistor in said first inverter; means for inputting a clock signal to an electrode of the transistor in said second inverter; a third transistor having its source connected to the saturable resistor associated with said second transistor, in said second inverter, and wherein the drain and gate electrode of said third transistor are connected between the saturable resistor of the first inverter and the transistor of the first inverter; and wherein the first inverter has at least one signal input and the output of said entire logic gate is taken at a common point between said saturable resistor associated with said second inverter and said third transistor; wherein the input of said triplet is in the input of said first gate, the output is the output of said second gate and wherein said third gate has an additional input means and wherein the output of said third gate is re-looped.

Claim 6

A triplet of logic gates according to claim 3 wherein the first gate of the sequence comprises an additional logic 1 resetting input and at least one additional re-looping input.

Claim 7

A sequential logic circuit comprising at least two series-mounted triplets of logic gates according to claim 3 wherein: the gate of the first triplet comprises an additional logic 1 resetting input and as many additional re-looping inputs as there are triplets in the sequence; the output of a triplet is linked to the input of the following triplet in the sequence; the re-looping outputs of the triplets of the sequence are each connected to a re-looping input of the first gate of the first triplet.

Claim 8

A sequential logic circuit according to claim 5 forming a programmable frequency divider circuit, an odd-numbered dividing ratio being obtained by placing the programming input of one of the triplets of the sequence at logic 0 level and the programming inputs of the other triplets of the sequence at logic 1 level.

Claim 9

A sequential logic circuit according to claim 5 comprising a programmable frequency divider circuit, an odd-numbered dividing ratio being obtained by placing two programming inputs of two neighbouring triplets in the sequence at logic 0 level and the programming inputs of the other triplets of the sequence at logic 1 level.

Claim 10

A sequential logic circuit according to claim 6 comprising a frequency divider circuit with a dividing ratio of 2n+1 by means of a single loop of 2n+1 coincidence gates, in which those triplets, the programming inputs of which are at logic 1 level, are non-looped.

Claim 11

A sequential logic circuit according to claim 7 comprising a frequency divider circuit with a dividing ratio of 2n by means of two loops with 2n-1 gates and 2n+1 gates.

Claim 12

A sequential logic circuit according to any one of the claims 5 to 9 wherein it is made in the form of an integrated circuit on fast material from the III-V group such as GaAs.