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Patent US4935868A successfully refreshed from Google Patents.
US4935868A
Expired / Lapsed
US
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Multiple port bus interface controller with slave bus
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1988-11-28
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Granted: 1990-06-19
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Expires: 2008-11-28
Abstract
Abstract A new integrated circuit for interfacing a standard IEEE 796 bus to a VSB-type buffer bus. This integrated circuit includes a DMA channel for high speed access of the IEEE 796 bus to the buffer bus, and a slave bus channel for high speed access of the buffer bus to the IEEE 796 bus. A third bus interface connects to a local processor to assist in arbitration and control during some types of data transfers.
Inventors
- 👤 Keith B. DuLac
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
249 words
An electronic apparatus for interfacing a plural bus that connects to a host processor unit and a plural bus unit, said plural bus having separate parallel address and data sub-buses, to a buffer bus that connects to an additional processor and a buffer bus unit, comprising: plural bus port means connected to said plural bus for directing a path of data transferred to said plural bus port means; buffer bus port means connected to said buffer bus of said additional processor unit for directing a path of data transferred to said buffer bus port means; data buffer means connected to said plural bus port means via a first data bus and to said buffer bus port means via a second data bus for buffering data transferred between said plural bus port means and said buffer bus port means via said first and second data buses; port control means connected to said plural bus port means via a first group of control lines, to said buffer bus port means via a second group of control lines, and to said data buffer means via a third set of control lines for controlling each transfer of data between said first data bus and said second data bus; and slave data bus means connected between said plural bus port means and said buffer bus port means for operating said buffer bus and said buffer bus unit, and said plural bus and said plural bus unit as a master-and-slave combination to transfer data therebetween.
Claim 2
Dependent Claim
249 words
An electronic apparatus for interfacing a plural bus that connects to a host processor unit and a plural bus unit, said plural bus having separate parallel address and data sub-buses, to a buffer bus that connects to an additional processor and a buffer bus unit, comprising: plural bus port means connected to said plural bus for directing a path of data transferred to said plural bus port means; buffer bus port means connected to said buffer bus of said additional processor unit for directing a path of data transferred to said buffer bus port means; data buffer means connected to said plural bus port means via a first data bus and to said buffer bus port means via a second data bus for buffering data transferred between said plural bus port means and said buffer bus port means via said first and second data buses; port control means connected to said plural bus port means via a first group of control lines, to said buffer bus port means via a second group of control lines, and to said data buffer means via a third set of control lines for controlling each transfer of data between said first data bus and said second data bus; and slave data bus means connected between said plural bus port means and said buffer bus port means for operating said buffer bus and said buffer bus unit, and said plural bus and said plural bus unit as a master-and-slave combination to transfer data therebetween.
Claim 3
Dependent Claim
41 words
The electronic apparatus of claim 1, further comprising a microprocessor connected to said electronic apparatus via a microprocessor bus for setting up said port control means before said transfer of data from said first data bus and said second data bus.
Claim 4
Dependent Claim
21 words
The electronic apparatus of claim 2, wherein said data is in a form of data words having eight data bits therein.
Claim 5
Dependent Claim
16 words
The electronic apparatus of claim 3, wherein said electronic apparatus is a single integrated circuit chip.
Claim 6
Dependent Claim
20 words
The electronic apparatus of claim 1, wherein said buffer bus unit and said additional processor unit are the same unit.
Claim 7
Dependent Claim
20 words
The electronic apparatus of claim 1, wherein said plural bus unit and said host processor unit are the same unit.
Claim 8
Dependent Claim
15 words
The electronic apparatus of claim 1, wherein said plural bus is an IEEE 796 buss.
Claim 9
Dependent Claim
33 words
The electronic apparatus of claim 7, wherein said buffer bus is a time division multiplexed bus having address information and data information transferred over common bus lines during different time division multiplex cycles.
Claim 10
Dependent Claim
16 words
The electronic apparatus of claim 1, wherein said data buffer means stores a digital data bit.
Claim 11
Dependent Claim
246 words
An electronic apparatus for interfacing a host processor unit having a plural bus connected thereto having separate parallel address and data sub-buses to a buffer bus unit having a buffer bus connected thereto, comprising: plural bus port means connected to said plural bus for directing a path of data transferred to said plural bus data port means; buffer bus port means connected to an additional processor unit via said buffer bus for directing a path of data transferred to said buffer bus port means; data buffer means connected to said plural bus port means via a first data bus and to said buffer bus port means via a second data bus for buffering data transferred between said plural bus port means and said buffer bus port means; port control means connected to said plural bus port means via a first group of control lines, to said buffer bus port means via a second group of control lines, and to said data buffer means via a third set of control lines for controlling a transfer of data between said first data bus and said second data bus; and slave data bus means connected between said plural bus port means and said buffer bus port means for operating said plural bus and said host processor unit connected thereto as a slave unit of said buffer bus and said buffer bus unit connected thereto as a master unit to transfer data between said master unit and said slave unit.
Claim 12
Dependent Claim
246 words
An electronic apparatus for interfacing a host processor unit having a plural bus connected thereto having separate parallel address and data sub-buses to a buffer bus unit having a buffer bus connected thereto, comprising: plural bus port means connected to said plural bus for directing a path of data transferred to said plural bus data port means; buffer bus port means connected to an additional processor unit via said buffer bus for directing a path of data transferred to said buffer bus port means; data buffer means connected to said plural bus port means via a first data bus and to said buffer bus port means via a second data bus for buffering data transferred between said plural bus port means and said buffer bus port means; port control means connected to said plural bus port means via a first group of control lines, to said buffer bus port means via a second group of control lines, and to said data buffer means via a third set of control lines for controlling a transfer of data between said first data bus and said second data bus; and slave data bus means connected between said plural bus port means and said buffer bus port means for operating said plural bus and said host processor unit connected thereto as a slave unit of said buffer bus and said buffer bus unit connected thereto as a master unit to transfer data between said master unit and said slave unit.
Claim 13
Dependent Claim
41 words
The electronic apparatus of claim 10, further comprising a microprocessor connected to said electronic apparatus via a microprocessor bus for setting up said port control means before said transfer of data from said first data bus and said second data bus.
Claim 14
Dependent Claim
21 words
The electronic apparatus of claim 11, wherein said data is in a form of data words having eight data bits therein.
Claim 15
Dependent Claim
16 words
The electronic apparatus of claim 12, wherein said electronic apparatus is a single integrated circuit chip.
Claim 16
Dependent Claim
20 words
The electronic apparatus of claim 10, wherein said buffer bus unit and said additional processor unit are the same unit.
Claim 17
Dependent Claim
16 words
The electronic apparatus of claim 10, wherein said data buffer means stores a digital data bit.
Claim 18
Dependent Claim
246 words
An electronic apparatus for interfacing a host processor unit having a plural bus having separate parallel address and data sub-buses to a buffer bus unit having a buffer bus, comprising: plural bus port means connected to the plural bus of the host processor unit for directing a path of data transferred to said plural bus port means; buffer bus port means connected to an additional processor unit via said buffer bus for directing a path of data transferred to said buffer bus port means; data buffer means connected to said plural bus port means via a first data bus and to said buffer bus port means via a second data bus for buffering data transferred between said plural bus port means and said buffer bus port means; port control means connected to said plural bus port means via a first group of control lines, to said buffer bus port means via a second group of control lines, and to said data buffer means via a third set of control lines for controlling the transfer of data between said first data bus and said second data bus; and slave data bus means connected between said plural bus port means and said buffer bus port means for operating said buffer bus and said buffer bus unit connected thereto as a slave unit of said plural bus and a plural bus unit connected thereto as a master unit to transfer data between said master unit and said slave unit.
Claim 19
Dependent Claim
246 words
An electronic apparatus for interfacing a host processor unit having a plural bus having separate parallel address and data sub-buses to a buffer bus unit having a buffer bus, comprising: plural bus port means connected to the plural bus of the host processor unit for directing a path of data transferred to said plural bus port means; buffer bus port means connected to an additional processor unit via said buffer bus for directing a path of data transferred to said buffer bus port means; data buffer means connected to said plural bus port means via a first data bus and to said buffer bus port means via a second data bus for buffering data transferred between said plural bus port means and said buffer bus port means; port control means connected to said plural bus port means via a first group of control lines, to said buffer bus port means via a second group of control lines, and to said data buffer means via a third set of control lines for controlling the transfer of data between said first data bus and said second data bus; and slave data bus means connected between said plural bus port means and said buffer bus port means for operating said buffer bus and said buffer bus unit connected thereto as a slave unit of said plural bus and a plural bus unit connected thereto as a master unit to transfer data between said master unit and said slave unit.
Claim 20
Dependent Claim
41 words
The electronic apparatus of claim 16, further comprising a microprocessor connected to said electronic apparatus via a microprocessor bus for setting up said port control means before said transfer of data from said first data bus and said second data bus.
Claim 21
Dependent Claim
21 words
The electronic apparatus of claim 17, wherein said data is in a form of data words having eight data bits therein.
Claim 22
Dependent Claim
16 words
The electronic apparatus of claim 18, wherein said electronic apparatus is a single integrated circuit chip.
Claim 23
Dependent Claim
20 words
The electronic apparatus of claim 16, wherein said buffer bus unit and said additional processor unit are the same unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |