US4246637A
Expired / Lapsed
US
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Data processor input/output controller
Assignee: International Business Machines Corp
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Filing: 1978-06-26
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Granted: 1981-01-20
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Expires: 1998-06-26
Abstract
Abstract A data processor input/output controller which is particularly useful as a microcontroller for the transfer of data between a host processor and one or more peripheral input/output devices in a digital data processing system. This input/output (I/O) controller is a subchannel controller for offloading a goodly portion of the subchannel control function from the host processor. This I/O controller includes a microprocessor for assisting and supervising the controller internal operations. Also included in the controller is an automatic high-speed data bypass mechanism whereby data may be transferred from the host processor to the I/O device or vice versa without having to pass through the microprocessor and without requiring any intervention on the part of the microprocessor during such automatic transfer. Provision is made for enabling the microprocessor to perform other functions, such as the presentation of interrupts to the host processor and the servicing of additional I/O commands from the host processor concurrently with the transfer of data via the automatic bypass mechanism. This capability is particularly useful where two or more I/O devices are connected to the controller. The automatic bypass mechanism is constructed to communicate with the host processor in a cycle steal mode. A look-ahead mechanism is provided for more quickly issuing the cycle steal requests to the host processor when operating in the automatic bypass mode.
Inventors
- 👤 Lewis W. Brown
- 👤 Douglas R. Chisholm
- 👤 Jerry D. Dixon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:12
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/32
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
262 words
An input/output controller for transferring data between a host processor and one or more input/output units and comprising: first plural-bit data storage means for sending data to and receiving data from a host processor; second plural-bit data storage means for sending data to and receiving data from an input/ouput unit; a microprocessor for controlling input/output activities; circuitry for transferring data between the first data storage means and the microprocessor; circuitry for transferring data between the microprocessor and the second data storage means; a data transfer bus providing a direct data transfer connection between the first and second data storage means; selectively operative automatic transfer control circuitry coupled to the first and second data storage means and effective, when operative, for automatically and sequentially transferring multiple units of data between the host processor and an input/output unit via the first and second data storage means and the direct data transfer bus and without requiring any action on the part of the microprocessor, said automatic transfer control circuitry further including: first load signal generating circuitry operative during input data transfer operations for supplying load signals to the first storage means when the second storage means is not empty and the first storage means is not full; and second load signal generating circuitry operative during output data transfer operations for supplying load signals to the second storage means when the first storage means is not empty and the second storage means is not full; and auto mode circuit means responsive to a start-up signal from the microprocessor for rendering the automatic transfer control circuitry operative.
Claim 2
Dependent Claim
262 words
An input/output controller for transferring data between a host processor and one or more input/output units and comprising: first plural-bit data storage means for sending data to and receiving data from a host processor; second plural-bit data storage means for sending data to and receiving data from an input/ouput unit; a microprocessor for controlling input/output activities; circuitry for transferring data between the first data storage means and the microprocessor; circuitry for transferring data between the microprocessor and the second data storage means; a data transfer bus providing a direct data transfer connection between the first and second data storage means; selectively operative automatic transfer control circuitry coupled to the first and second data storage means and effective, when operative, for automatically and sequentially transferring multiple units of data between the host processor and an input/output unit via the first and second data storage means and the direct data transfer bus and without requiring any action on the part of the microprocessor, said automatic transfer control circuitry further including: first load signal generating circuitry operative during input data transfer operations for supplying load signals to the first storage means when the second storage means is not empty and the first storage means is not full; and second load signal generating circuitry operative during output data transfer operations for supplying load signals to the second storage means when the first storage means is not empty and the second storage means is not full; and auto mode circuit means responsive to a start-up signal from the microprocessor for rendering the automatic transfer control circuitry operative.
Claim 3
Dependent Claim
19 words
An input/output controller in accordance with claim 1 wherein the first data storage means is a plural-bit data register.
Claim 4
Dependent Claim
19 words
An input/output controller in accordance with claim 1 wherein the second data storage means is a plural-bit data register.
Claim 5
Dependent Claim
22 words
An input/output controller in accordance with claim 1 wherein both the first and the second data storage means are plural-bit data register.
Claim 6
Dependent Claim
103 words
An input/output controller in accordance with claim 4 wherein the automatic transfer control circuitry further includes: first status indicating circuitry responsive to host processor transfer indicative signals and to the first and second load signals for providing indications of the full/empty status of the first data register; second status indicating circuitry responsive to input/output unit transfer indicative signals and to the first and second load signals for providing indications of the full/empty status of the second data register; and circuitry for coupling the first and second status indicating circuitry to the first and second load signal generating circuitry for controlling the operation thereof.
Claim 7
Dependent Claim
80 words
An input/output controller in accordance with claim 1 wherein the automatic transfer control circuitry includes: input transfer control circuitry operative during input data transfer operations for automatically transferring data from the second data storage means to the first data storage means via the direct data transfer bus; and output transfer control circuitry operative during output data transfer operations for automatically transferring data from the first data storage means to the second data storage means via the direct data transfer bus.
Claim 8
Dependent Claim
39 words
An input/output controller in accordance with claim 6 and further including circuitry operative when the automatic output transfer control circuitry is operative for supplying service requests to the host processor when the first data storage means is not full.
Claim 9
Dependent Claim
69 words
An input/output controller in accordance with claim 6 and further including: circuitry operative when the automatic input transfer control circuitry is operative for supplying service requests to the host processor when the second data storage means is not empty; and circuitry operative when the automatic input transfer control circuitry is operative for delaying acceptance of input data by the host processor if the first data storage means is empty.
Claim 10
Dependent Claim
76 words
An input/output controller in accordance with claim 6 wherein: both the first and the second data storage means are plural-bit data registers for holding a plural-bit unit of data; and the controller includes a lookahead mechanism operative during automatic input data transfer operations for sending service requests to the host processor before each unit of data being transferred is passed from the second data register to the first data register via the direct data transfer bus.
Claim 11
Dependent Claim
98 words
An input/output controller in accordance with claim 1 wherein the host processor includes a main storage unit and the input/output controller further includes: plural-bit address counter circuitry for supplying plural-bit main storage addresses to the host processor when the automatic transfer control circuitry is operative; circuitry for enabling the microprocessor to load a starting main storage address into the address counter circuitry before the commencement of automatic data transfer operations; and circuitry for automatically incrementing the address counter circuitry as each unit of data is transferred to or from the host processor during the automatic data transfer operations.
Claim 12
Dependent Claim
70 words
An input/output controller in accordance with claim 1 and further including: third plural-bit data storage means for transferring command information from the host processor to the microprocessor concurrently with the automatic transfer of data via the direct data transfer bus; and fourth plural-bit data storage means for transferring interrupt information from the microprocessor to the host processor concurrently with the automatic transfer of data via the direct data transfer bus.
Claim 13
Dependent Claim
269 words
An input/output controller for transferring data between a host processor and one or more input/output units and comprising: interface connection means for coupling the input/output controller to a host processor input/output interface bus; a microprocessor located in the input/output controller for controlling input/output activities; first plural-bit register means coupled to the interface connection means for sending data to and receiving data from the host processor; second plural-bit register means for sending data to and receiving data from an input/output unit; automatic data transfer circuitry coupled to the first register means for automatically transferring data between the host processor and an input/output unit via the first register means and independently of the microprocessor, said automatic transfer control circuitry further including: first load signal generating circuitry operative during input data transfer operations for supplying load signals to the first register means when the second register means is full and the first register means is empty; and second load signal generating circuitry operative sduring output data transfer operations for supplying load signals to the second register means when the first register means is full and the second register means is empty; third plural-bit register means coupled to the interface connection means and to the microprocessor for receiving host processor command information and supplying same to the microprocessor concurrently with the automatic transfer of data via the automatic data transfer circuitry; and fourth plural-bit register means coupled to the interface connection means and to the microprocessor for receiving interrupt information from the microprocessor and supplying same to the host processor concurrently with the automatic transfer of data via the automatic data transfer circuitry.
Claim 14
Dependent Claim
269 words
An input/output controller for transferring data between a host processor and one or more input/output units and comprising: interface connection means for coupling the input/output controller to a host processor input/output interface bus; a microprocessor located in the input/output controller for controlling input/output activities; first plural-bit register means coupled to the interface connection means for sending data to and receiving data from the host processor; second plural-bit register means for sending data to and receiving data from an input/output unit; automatic data transfer circuitry coupled to the first register means for automatically transferring data between the host processor and an input/output unit via the first register means and independently of the microprocessor, said automatic transfer control circuitry further including: first load signal generating circuitry operative during input data transfer operations for supplying load signals to the first register means when the second register means is full and the first register means is empty; and second load signal generating circuitry operative sduring output data transfer operations for supplying load signals to the second register means when the first register means is full and the second register means is empty; third plural-bit register means coupled to the interface connection means and to the microprocessor for receiving host processor command information and supplying same to the microprocessor concurrently with the automatic transfer of data via the automatic data transfer circuitry; and fourth plural-bit register means coupled to the interface connection means and to the microprocessor for receiving interrupt information from the microprocessor and supplying same to the host processor concurrently with the automatic transfer of data via the automatic data transfer circuitry.
Claim 15
Dependent Claim
36 words
An input/output controller in accordance with claim 12 and further including circuitry for enabling the microprocessor to provide an initial set-up of the automatic data transfer circuitry before commencement of automatic transfer operations by such circuitry.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-20 | 1984-07-21 | 1985-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-20 | 1988-07-21 | 1989-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-20 | 1992-07-21 | 1993-01-20 | $7700.00 | Window Closed / Lapsed |