Multiple port bus interface controller with slave bus

Claim 1

An electronic apparatus for interfacing a plural bus that connects to a host processor unit and a plural bus unit, said plural bus having separate parallel address and data sub-buses, to a buffer bus that connects to an additional processor and a buffer bus unit, comprising: plural bus port means connected to said plural bus for directing a path of data transferred to said plural bus port means; buffer bus port means connected to said buffer bus of said additional processor unit for directing a path of data transferred to said buffer bus port means; data buffer means connected to said plural bus port means via a first data bus and to said buffer bus port means via a second data bus for buffering data transferred between said plural bus port means and said buffer bus port means via said first and second data buses; port control means connected to said plural bus port means via a first group of control lines, to said buffer bus port means via a second group of control lines, and to said data buffer means via a third set of control lines for controlling each transfer of data between said first data bus and said second data bus; and slave data bus means connected between said plural bus port means and said buffer bus port means for operating said buffer bus and said buffer bus unit, and said plural bus and said plural bus unit as a master-and-slave combination to transfer data therebetween.