Semiconductor memory device for reducing power dissipation during a write operation

Claim 1

A semiconductor memory device for reducing power dissipation during a write operation, comprising: a memory cell array including a plurality of static RAM type memory cells arranged in rows and columns; a first bit line and a second bit line for each column of said memory cell array, the memory cells of each column being coupled between said first and second bit lines; first and second data write circuits coupled to said first and second bit lines, respectively; first and second column select switches for each column of said memory array, each said first column select switch being coupled in series with said first bit line between said first data write circuit and said memory cells, and each said second column select switch being coupled in series with said second bit line between said second data write circuit and said memory cells; bit-line load circuits respectively associated with the columns of said memory cell array, each said bit-line load circuit being coupled to said first and second bit lines between each of said first and second column select switches and said memory cells; and means for applying a control signal to said bit-line load circuit to disable said bit-line load circuit when the column associated with said bit-line load circuit includes one of said memory cells that is in a write mode and the column is selected and for enabling said bit-line load circuit at other times.