Write circuit for a read/write memory

Claim 2

A write circuit for a read/write memory, comprising: transferring means for controllably transferring data from a data in buffer into the write circuit; isolation means coupled to the transferring means to isolate an address signal from the transferring means, the isolation means also being capable of controlling the transferring means; precharging means for controllably discharging the output of the transferring means; control means coupled to the precharging means for controlling the precharging means; and latching means coupled to the output of the transferring means for coupling the output of the transferring means into the memory.

Claim 3

The write circuit of claim 1 wherein the control means includes field effect transistors connected in series with each having a gate electrode for receiving a control signal.

Claim 4

The write circuit of claim 1 wherein the isolation means includes at least one field effect transistor having a first, a second, and a gate electrode, the gate electrode being coupled to a voltage potential, the first electrode being coupled to a select signal and the second electrode being coupled to the transferring means.

Claim 5

The write circuit of claim 1 wherein the transferring means comprises a field effect transistor having a first and a second current carrying electrode and a gate electrode, the gate electrode being coupled to the isolation means so that the isolation means can control the transferring means, the first current carrying electrode being coupled to the data in buffer, and the second current carrying electrode being for providing the output.

Claim 6

A circuit for controllably coupling data from an input buffer into a system, the circuit having a first and a second voltage terminal, comprising: a first and a second transistor for coupling data and its complement from the input buffer into the circuit; a third and a fourth transistor coupled in series between gate electrodes of the first and second transistors, the third and fourth transistors having gate electrodes coupled to the first voltage terminal and a first select signal coupled to a junction formed in between the third and fourth transistors; a fifth transistor having a gate electrode and being coupled between the first transistor and the second voltage terminal; a sixth transistor having a gate electrode and being coupled between the second transistor and the second voltage terminal; a seventh and an eighth transistor coupled in series between the first and second voltage terminal, and each transistor having a gate electrode; a ninth and a tenth transistor coupled in series between the first and second voltage terminals and each transistor having a gate electrode, the gate electrode of the seventh and tenth transistors being coupled to the first transistor and the gate electrodes of the ninth and eighth transistors being coupled to the second transistor; and a control signal coupled to the gate electrodes of the fifth and sixth transistors.

Claim 7

A circuit for controllably coupling data from an input buffer into a system, the circuit having a first and a second voltage terminal, comprising: a first and a second transistor for coupling data and its complement from the input buffer into the circuit; a third and a fourth transistor coupled in series between gate electrodes of the first and second transistors, the third and fourth transistors having gate electrodes coupled to the first voltage terminal and a first select signal coupled to a junction formed in between the third and fourth transistors; a fifth transistor having a gate electrode and being coupled between the first transistor and the second voltage terminal; a sixth transistor having a gate electrode and being coupled between the second transistor and the second voltage terminal; a seventh and an eighth transistor coupled in series between the first and second voltage terminal, and each transistor having a gate electrode; a ninth and a tenth transistor coupled in series between the first and second voltage terminals and each transistor having a gate electrode, the gate electrode of the seventh and tenth transistors being coupled to the first transistor and the gate electrodes of the ninth and eighth transistors being coupled to the second transistor; and a control signal coupled to the gate electrodes of the fifth and sixth transistors.

Claim 8

The circuit of claim 5 wherein the seventh and eighth transistors form a node therebetween which provides a first output for the circuit, and the ninth and tenth transistors forming a node therebetween which provides a second output for the circuit, the first and second outputs being complements of each other.

Claim 9

The circuit of claim 5 further including transistors coupled in series between the first and second voltage terminal, and each transistor having a gate to receive a select signal so that the transistors coupled in series can provide the control signal to control the fifth and sixth transistors.

Claim 10

The circuit of claim 5 wherein a first and a second such circuits are used for coupling data into a binary memory system and the first select signal is used to enable the first such circuit for coupling data into the memory and a complement of the first select signal is used to enable the second such circuit.