US4160291A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Precharge circuitry for an electrically alterable non-volatile memory
Assignee: Micron Technology Inc
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Filing: 1978-07-31
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Granted: 1979-07-03
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Expires: 1998-07-31
Abstract
Abstract An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.
Inventors
- 👤 Philip C. Smith
- 👤 John L. Fagan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:51
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C11/00; G11C11/21; G11C11/26; G11C11/30; G11C16/04; G11C16/0466; G11C5/00; G11C5/02; G11C5/025; G11C8/00; G11C8/10; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
224 words
A non-volatile semiconductor memory array row decoder for precharging a plurality of rows of memory cells in said array at a first time and for selecting one of said rows at a second time following said first time comprising, a first circuit node, a plurality of circuit paths from said first circuit node to each of said rows, each of said circuit paths including a plurality of field effect transistors, each having a gate, source and drain electrode, connected in series between the source and drain electrodes, means for coupling a plurality of address signals to said gates of said transistors to cause one circuit path to conduct current in response to said plurality of address signals, each address signal may be represented by its true or complement level, means for coupling said first circuit node to a first supply voltage in response to a write signal, means for coupling said first circuit node to a second supply voltage in response to a read signal, and means for coupling said first circuit node to a third supply voltage in response to a reset signal to precharge to a predetermined voltage through said plurality of said circuit paths, said plurality of rows at times when the potential of said plurality of address signals are all at a voltage to cause said transistors to conduct current.
Claim 2
Dependent Claim
224 words
A non-volatile semiconductor memory array row decoder for precharging a plurality of rows of memory cells in said array at a first time and for selecting one of said rows at a second time following said first time comprising, a first circuit node, a plurality of circuit paths from said first circuit node to each of said rows, each of said circuit paths including a plurality of field effect transistors, each having a gate, source and drain electrode, connected in series between the source and drain electrodes, means for coupling a plurality of address signals to said gates of said transistors to cause one circuit path to conduct current in response to said plurality of address signals, each address signal may be represented by its true or complement level, means for coupling said first circuit node to a first supply voltage in response to a write signal, means for coupling said first circuit node to a second supply voltage in response to a read signal, and means for coupling said first circuit node to a third supply voltage in response to a reset signal to precharge to a predetermined voltage through said plurality of said circuit paths, said plurality of rows at times when the potential of said plurality of address signals are all at a voltage to cause said transistors to conduct current.
Claim 3
Dependent Claim
133 words
An electrically alterable non-volatile semiconductor array for storing information comprising: a plurality of memory cells arranged in rows and columns to form said array, each of said memory cells comprising at least one variable threshold field effect transistor, the drain electrodes of one transistor per memory cell in a column of memory cells coupled together, the source electrodes of said one transistor per memory cell in said column of memory cells coupled together, first means for precharging to a potential the gates of said transistors at times prior to reading information from said array, second means for precharging to a potential the source and drain electrodes of said transistors at times prior to reading information from said array, means for writing information into said array; and means for reading information from said array.
Claim 4
Dependent Claim
133 words
An electrically alterable non-volatile semiconductor array for storing information comprising: a plurality of memory cells arranged in rows and columns to form said array, each of said memory cells comprising at least one variable threshold field effect transistor, the drain electrodes of one transistor per memory cell in a column of memory cells coupled together, the source electrodes of said one transistor per memory cell in said column of memory cells coupled together, first means for precharging to a potential the gates of said transistors at times prior to reading information from said array, second means for precharging to a potential the source and drain electrodes of said transistors at times prior to reading information from said array, means for writing information into said array; and means for reading information from said array.
Claim 5
Dependent Claim
57 words
The electrically alterable non-volatile semiconductor array of claim 2 wherein said second means for precharging includes a field effect transistor having a source and drain coupled across said source and drains of said transistors and having its gate coupled to a control signal for causing said field effect transistor to conduct current at times prior to reading.
References Cited (Backward Citations)
US4091360A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-07-02 | 1983-01-01 | 1983-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-07-02 | 1987-01-01 | 1987-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-07-02 | 1991-01-01 | 1991-07-03 | $7700.00 | Window Closed / Lapsed |