Bit line driver

Claim 2

A bit line driver connected between a pair of complementary bit lines and having an equalizing MOS transistor for effecting equalization operation by shorting a pair of the complementary bit lines in response to a clock pulse applied to a gate of the equalizing MOS transistor, which comprises: (a) a pair of active-load MOS transistors, each respectively connected between one of the complementary bit lines and a power supply, a gate of each of said active-load MOS transistors being connected to ground; and (b) a pair of clamping MOS transistors each respectively connected in parallel to one of said active-load MOS transistors, each of said clamping MOS transistors being diode connected; wherein the area of said clamping MOS transistors is about three times greater than that of said active-load MOS transistors and the equalizing MOS transistor.

Claim 3

The bit line driver as set forth in claim 1, wherein said equalizing MOS transistor, said pair of active-load MOS transistors and said pair of clamping MOS transistors are all P-channel type, a drain of each of said pair of active-load P-channel MOS transistors being respectively connected to one of a pair of the complementary bit lines; a source of each of said pair of active-load P-channel MOS transistors being connected to the power supply; and each drain and each source of said pair of clamping P-channel MOS transistors being connected in parallel to each drain and each source of said pair of active-load P-channel MOS transistors.

Claim 4

In a memory circuit which includes a pair of complementary bit lines, a power supply source, and a clock pulse source, together in circuit with an equalizing MOS transistor having a source and a drain in circuit with said complementary bit lines for effecting an equalization operation in response to a clock pulse applied to a gate of the equalizing MOS transistor, a combination which comprises: (a) a first clamping MOS transistor which includes a source in circuit with said power supply, a gate in circuit with a drain of said first clamping MOS transistor, said gate and said drain being in circuit with the source to drain path of said equalizing MOS transistor; (b) a first active load MOS transistor which includes a source in circuit with said power supply, a grounded gate, and a drain in circuit with the gate and drain of said first clamping MOS transistor and said source to drain path of said equalizing MOS transistor; (c) a second active load MOS transistor which includes a source in circuit with said power supply, a grounded gate, and a drain in circuit with the source to drain path of said equalizing transistor; and (d) a second clamping MOS transistor which includes a source connected to said power supply, a gate connected to a drain of said second clamping MOS transistor, said gate and said drain of said second clamping MOS transistor being in circuit with the source to drain path of said equalizing transistor and with the drain of said second active load MOS transistor; wherein the area of at least one of the first and second clamping MOS transistors is at least three times greater than the area of the first and the second active-load MOS transistors and the equalizing MOS transistor, so that the resistance of said clamping MOS transistors is relatively low, whereby the rate of change of potential during switching on said complementary bit lines is increased, thus shortening access time.

Claim 5

In a memory circuit which includes a pair of complementary bit lines, a power supply source, and a clock pulse source, together in circuit with an equalizing MOS transistor having a source and a drain in circuit with said complementary bit lines for effecting an equalization operation in response to a clock pulse applied to a gate of the equalizing MOS transistor, a combination which comprises: (a) a first clamping MOS transistor which includes a source in circuit with said power supply, a gate in circuit with a drain of said first clamping MOS transistor, said gate and said drain being in circuit with the source to drain path of said equalizing MOS transistor; (b) a first active load MOS transistor which includes a source in circuit with said power supply, a grounded gate, and a drain in circuit with the gate and drain of said first clamping MOS transistor and said source to drain path of said equalizing MOS transistor; (c) a second active load MOS transistor which includes a source in circuit with said power supply, a grounded gate, and a drain in circuit with the source to drain path of said equalizing transistor; and (d) a second clamping MOS transistor which includes a source connected to said power supply, a gate connected to a drain of said second clamping MOS transistor, said gate and said drain of said second clamping MOS transistor being in circuit with the source to drain path of said equalizing transistor and with the drain of said second active load MOS transistor; wherein the area of at least one of the first and second clamping MOS transistors is at least three times greater than the area of the first and the second active-load MOS transistors and the equalizing MOS transistor, so that the resistance of said clamping MOS transistors is relatively low, whereby the rate of change of potential during switching on said complementary bit lines is increased, thus shortening access time.

Claim 6

The combination as set forth in claim 3, wherein said equalizing MOS transistor, each of said active-load MOS transistors, and each of said first and said second clamping MOS transistors are P-channel type transistors, said first clamping MOS transistor and said first active load MOS transistor being connected to one of a pair of the complementary bit lines, said second clamping MOS transistor and said second active load transistor being connected to the other of said pair of said complementary bit lines.

Claim 7

The combination as set forth in claim 4, wherein said complementary bit lines are connected to a read amplifier for reading data in a memory cell accessed by a signal on a word line.

Claim 8

A bit line driver connected between a pair of complementary bit lines and having an equalizing MOS transistor for effecting equalization operation by shorting a pair of the complementary bit lines in response to a clock pulse applied to a gate of the equalizing MOS transistor, which comprises: (a) a pair of active-load MOS transistors, each respectively connected between one of the complementary bit lines and a power supply, a gate of each of said active-load MOS transistor being connected to a common connection; and (b) a pair of clamping MOS transistors each respectively connected in parallel to one of said active-load MOS transistors, each of said clamping MOS transistors being diode connected, each of said clamping transistors having an area at least about three times greater than that of said active-load MOS transistors and said equalizing MOS transistor.

Claim 9

A bit line driver connected between a pair of complementary bit lines and having an equalizing MOS transistor for effecting equalization operation by shorting a pair of the complementary bit lines in response to a clock pulse applied to a gate of the equalizing MOS transistor, which comprises: (a) a pair of active-load MOS transistors, each respectively connected between one of the complementary bit lines and a power supply, a gate of each of said active-load MOS transistor being connected to a common connection; and (b) a pair of clamping MOS transistors each respectively connected in parallel to one of said active-load MOS transistors, each of said clamping MOS transistors being diode connected, each of said clamping transistors having an area at least about three times greater than that of said active-load MOS transistors and said equalizing MOS transistor.

Claim 10

The bit line driver as set forth in claim 6, wherein said common gate connection of said pair of active-load MOS transistors is grounded.

Claim 11

The bit line driver as set forth in claim 6, wherein said equalizing MOS transistor, said pair of active-load MOS transistors and said pair of clamping MOS transistors are all P-channel type transistors.