Bit line load and column circuitry for a semiconductor memory

Claim 2

A bit line load for a semiconductor memory characterised in that the bit line load (10) comprises a bit line clamp circuit (30) coupled to the bit line (14), and a substantially constant current source (32) coupled to the bit line (14) and to the bit line clamp (30).

Claim 3

A bit line load as claimed in claim 1, wherein the bit line clamp (10) includes an N-channel transistor (30) having a drain and gate coupled to a source of operating voltage (YCC).

Claim 4

A bit line load as claimed in claim 1 wherein said current source includes a P-channel transistor (32) coupled to a reference voltage source (VR1).

Claim 5

A bit line load as claimed in claim 3 wherein the source of said P-channel transistor (32) is coupled to the bit line (14), its drain is coupled to a source of operating voltage (VCC), and its gate is coupled to said reference voltage source (VR1).

Claim 6

A bit line load as claimed in any preceding claim, including a voltage source (VR1) to provide a reference which tracks changes in semiconductor circuitry.

Claim 7

A bit line load as claimed in claim 5, wherein said reference voltage source (VR1) includes means for modelling the characteristics of transistors in the bit line load.

Claim 8

A bit line load as claimed in claim 5 or 6, wherein the bit line load includes both N-channel and P-channel transistors (30,32) and wherein said reference voltage source (VR1) includes P-channel and N-channel transistors.

Claim 9

A bit line load as claimed in claim 7, wherein said reference voltage source (VR1) includes an output node (85) coupled to N-channel and P-channel transistors on the same chip as the bit line load.

Claim 10

A bit line load as claimed in claim 8 wherein said reference voltage source (VR1) includes a self-biased inverter including a P-channel transistor and an N-channel transistor.

Claim 11

A bit line load as claimed in claim 8 or 9, wherein said reference voltage source (VR1) is compensated for changes in characteristics of transistors coupled to the bit line load.

Claim 12

A bit line load as claimed in any preceding claim, including means for compensating said current source (32) for changes in transistors coupled to the bit line load.

Claim 13

A bit line load as claimed in any preceding claim, including means for compensating said current source (32) for changes in memory cell transistors coupled to the bit lines.

Claim 14

A bit line load as claimed in any preceding claim, wherein said bit line clamp includes a clamp transistor (30) whose source-drain path couples a source of voltage to the bit line when said transistor is on.

Claim 15

A semiconductor memory comprising first and second bit lines (14,16) having an addressable memory cell (12) therebetween, a selectively operable equilibration means (34) for substantially equalising the voltages on the bit lines at an equalised voltage level, and a bit line load as claimed in any preceding claim coupled to each bit line, the bit line clamp circuit (30) of the respective bit line load including a clamp transistor (30) whose source-drain path couples a source of voltage (YCC) to the bit line (14) when said transistor (30) is on, said clamp transistor (30) being configured so that it does not turn on when its source is at said equalised voltage despite its gate and drain being at a high level, whereby if the memory cell (12) pulls said bit line to a lower voltage after said equalising occurs, said clamp transistor turns on to clamp said bit line to a voltage.

Claim 16

A semiconductor memory having rows and columns of memory cells, each column having a pair of bit lines (14,16) coupled to memory cells (12) in the column, and having column circuitry comprising a pair of data read lines (24,26) associated with plural columns of memory cells; and, in each column, a respective differential amplifier arrangement (40) coupled to said data read lines and compensated for changes in transistor characteristics.

Claim 17

A semiconductor memory having rows and columns of memory cells, each column having a pair of bit lines (14,16) coupled to memory cells (12) in the column, and having column circuitry comprising a pair of data read lines (24,26) associated with plural columns of memory cells; and, in each column, a respective differential amplifier arrangement (40) coupled to said data read lines and compensated for changes in transistor characteristics.

Claim 18

A semiconductor memory as claimed in claim 15, further including a current source (48,50) having a pair of transistors whose source-drain paths selectively couple a source of operating voltage (VCC) to said data read lines, and whose gates are coupled to a voltage reference (VR2).

Claim 19

A semiconductor memory as claimed in claim 15 or 16, further including separate write lines (20,22), means (62,64) coupling said write lines to the bit lines (14,16), and means for activating said coupling means.

Claim 20

A semiconductor memory as claimed in any of claims 14 to 17, wherein each of said differential amplifier arrangements (40) includes a differential amplifier having input transistors (42,44) and a current source (46) coupled thereto and wherein said column circuitry further includes a switching means (52,54) coupled to the gate of said current source (46) and to a column selection input means for receiving a signal for activating the column.

Claim 21

A semiconductor memory as claimed in claim 18, wherein said differential amplifier arrangement (40) includes means for compensating for transistor changes, said means being coupled to said current source (46) and including means for modelling the characteristics of transistors in the column circuitry.

Claim 22

A semiconductor memory as claimed in claim 18 or 19, wherein each of said input transistors (42,44) has a source-drain path coupled to a respective data read line (24,26) and a common node (60) between said input transistors, said column circuitry further including means for coupling together the pair of bit lines in each non-seclected column.

Claim 23

A semiconductor memory as claimed in claim 20, wherein said means for coupling includes for each column, a respective transistor (42,44) whose source-drain path selectively couples one line of the pair of bit lines to the other bit line of the pair, said transistors being responsively coupled to an address signal.

Claim 24

A semiconductor memory having rows and columns of memory cells, each column having a pair of bit lines (14,16) coupled to memory cells (12) in the column, and having column circuitry comprising a pair of data read lines (24,26) associated with plural columns of memory cells, and a current source (48,50) coupled to said data read lines and compensated for changes in transistor characteristics.

Claim 25

A semiconductor memory having rows and columns of memory cells, each column having a pair of bit lines (14,16) coupled to memory cells (12) in the column, and having column circuitry comprising a pair of data read lines (24,26) associated with plural columns of memory cells, and a current source (48,50) coupled to said data read lines and compensated for changes in transistor characteristics.

Claim 26

A semiconductor memory as claimed in claim 22, wherein said current source includes a transistor coupled to receive a variable reference voltage (YR2).

Claim 27

A semiconductor memory as claimed in claim 22 or 23, wherein said current source comprises a respective transistor (48,50) for each data read line, the source-drain path of each coupled between its corresponding data read line and a source (VCC) of operating voltage, each of said transistors having a gate coupled to a variable reference voltage (YR2) provided by circuitry including means for modelling the characteristics of transistors in the column circuitry.

Claim 28

A semiconductor memory as claimed in any of claims 22 to 24, wherein said current source (48,50) includes means for compensating for changes in characteristics of transistors in the column circuitry.

Claim 29

A semiconductor memory as claimed in claim 25, wherein said column circuitry includes P-channel and N-channel transistors, and wherein said means for compensating is located on the same chip as said column circuitry and models both P-channel and N-channel transistors.

Claim 30

A semiconductor memory as claimed in claim 25 or 26, including a VCC protection circuit (Figure 4) coupled to a data read line and including: a transistor coupled to VCC and to said means for compensating so that said transistor (136) turns on as VCC drops; and means responsive to said transistor entering saturation to couple said data line to VCC.

Claim 31

A semiconductor memory having plural columns of memotry cells, each column having a pair of bit lines coupled to the memory cells in the column, and having column circuitry including: plural current sources coupled so that each bit line is coupled to a first compensated reference; plural bit line clamps, each bit line being coupled to a bit line clamp, each of said clamps coupling a source of operating voltage to its bit line when the clamp is in an operative state; a pair of data read lines corresponding to a plurality of bit line pairs; plural pairs of input transistors, each gated by a corresponding bit line and each selectively coupling a data read line to a common node between each pair of input transistors; plural differential amplifiers each corresponding to a pair of bit lines, said differential amplifiers each including said input transistors; a current source load coupled to said data read lines and coupled to a second compensated reference; and plural sneak capacitance reduction means each coupled to a pair of bit lines, each being responsive to a column select signal to couple the bit line pair together to permit the memory cell therebetween to pull both bit lines to a low voltage thereby to isolate said data read lines from their corresponding common nodes except in the selected column.

Claim 32

A semiconductor memory having plural columns of memotry cells, each column having a pair of bit lines coupled to the memory cells in the column, and having column circuitry including: plural current sources coupled so that each bit line is coupled to a first compensated reference; plural bit line clamps, each bit line being coupled to a bit line clamp, each of said clamps coupling a source of operating voltage to its bit line when the clamp is in an operative state; a pair of data read lines corresponding to a plurality of bit line pairs; plural pairs of input transistors, each gated by a corresponding bit line and each selectively coupling a data read line to a common node between each pair of input transistors; plural differential amplifiers each corresponding to a pair of bit lines, said differential amplifiers each including said input transistors; a current source load coupled to said data read lines and coupled to a second compensated reference; and plural sneak capacitance reduction means each coupled to a pair of bit lines, each being responsive to a column select signal to couple the bit line pair together to permit the memory cell therebetween to pull both bit lines to a low voltage thereby to isolate said data read lines from their corresponding common nodes except in the selected column.