US4931667A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for a dual bus line
Assignee: US Philips Corp
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Filing: 1988-11-02
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Granted: 1990-06-05
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Expires: 2008-11-02
Abstract
Abstract Data are frequently transmitted via a dual bus line by means of differential signals which are evaluated by a differential amplifier, particularly for reasons of protection against interference. However, such a differential amplifier only has a limited input voltage range, or a dead voltage range of the input signals within which it is not capable of operating. To prevent the voltages on both bus lines from getting into this dead voltage range, either due to a common-mode interference signal on the bus lines or due to a voltage dip in the feed voltage of the differential amplifier, the two bus lines are connected in accordance with the invention to an adjusting circuit which changes the voltages of both bus lines by the same amount in the direction out of the dead voltage range. This prevents unspecified conditions of the differential amplifier without significantly influencing the differential signal on the two bus lines. The application for an integrated memory is described.
Inventors
- 👤 Leonardus C. M. G. Pfennings
- 👤 Peter H. Voss
- 👤 Cormac M. O'Connell
- 👤 Cathal G. Phelan
- 👤 Thomas J. Davies
- 👤 Hans Ontrop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:40
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
190 words
A circuit arrangement for a dual bus line for the transmission of differential signal voltages, each individual bus line of which is connected to a different input of a different amplifier which is connected to a first pole and to a second pole of a feed voltage and the operating capability of which is restricted if the voltages at the two inputs are within a dead voltage range which is limited by the voltage at one pole of the feed voltage and by a voltage between the two poles, characterized in that an adjusting circuit is provided which is connected to both bus lines and contains (a) detector means for generating a control signal at a control output if the voltages on both bus lines are simultaneously within the dead voltage range, and (b) a drive circuit, which is connected to both bus lines and responds to the control signal in order to change the voltages on both bus lines by essentially the same amount in the direction of the voltage at the other pole until the voltage on at least one bus line is outside the dead voltage range.
Claim 2
Dependent Claim
190 words
A circuit arrangement for a dual bus line for the transmission of differential signal voltages, each individual bus line of which is connected to a different input of a different amplifier which is connected to a first pole and to a second pole of a feed voltage and the operating capability of which is restricted if the voltages at the two inputs are within a dead voltage range which is limited by the voltage at one pole of the feed voltage and by a voltage between the two poles, characterized in that an adjusting circuit is provided which is connected to both bus lines and contains (a) detector means for generating a control signal at a control output if the voltages on both bus lines are simultaneously within the dead voltage range, and (b) a drive circuit, which is connected to both bus lines and responds to the control signal in order to change the voltages on both bus lines by essentially the same amount in the direction of the voltage at the other pole until the voltage on at least one bus line is outside the dead voltage range.
Claim 3
Dependent Claim
90 words
An integrated circuit arrangement for processing digital data, having a circuit arrangement according to claim 1, wherein the dual bus line is a data line which extends over a significant physical distance within the integrated circuit arrangement to said differential amplifier, the voltage on both individual bus lines being temporarily brought to at least a value in the immediate vicinity of one limit of the dead voltage range via a precharge circuit, and the detector means and the driver circuit being arranged in the physical vicinity of said differential amplifier.
Claim 4
Dependent Claim
116 words
An integrated circuit according to claim 2, wherein the detector means comprise two first enhancement-type MOS transistors which are connected in parallel between one pole of the feed voltage and the control output and the gates of which are connected to the bus lines, the control output being connected to the other pole of the feed voltage via a resistor arrangement, and that the driver circuit exhibits two second enhancement-type MOS transistors of the opposite type of conductivity to the first transistors which are in each case arranged between one bus line and the other pole of the feed voltage and the gates of which are controlled by the control signal via an MOS inverter circuit.
Claim 5
Dependent Claim
46 words
An integrated circuit according to claim 3, wherein the inverter circuit is constructed as an inverting CMOS gate having a switching input and wherein said differential amplifier switchably disables said switch input, said differential amplifier and said switching input being controlled by a common switching signal.
Claim 6
Dependent Claim
78 words
An integrated circuit according to claim 3, wherein the resistor arrangement in a third enhancement-type MOS transistor of the same type conductivity as the second transistors, with a width/length ratio which is smaller than that of the first transistors, that fourth enhancement-type MOS transistor of the same type of conductivity as the first transistors is arranged in parallel with the first transistors and the gates of the third and fourth transistor are controlled by a detector switching signal.
Claim 7
Dependent Claim
61 words
An integrated circuit according to claim 3, having such a small structure that hot electrons can occur in a plurality of first selected transistors, wherein a further transistor, a gate of which is connected to a fixed bias voltage, si connected between said first selected transistors and a plurality of second selected transistors connected to said poles of the feed voltage.
Claim 8
Dependent Claim
79 words
An integrated circuit according to claim 4, wherein the resistor arrangement is a third enhancement-type MOS transistor of the same type conductivity as the second transistors, with a width/length ratio which is smaller than that of the first transistors, that a fourth enhancement-type MOS transistor of the same type of conductivity as the first transistors is arranged in parallel with the first transistors and the gates of the third and fourth transistor are controlled by a detector switching signal.
Claim 9
Dependent Claim
61 words
An integrated circuit according to claim 4, having such a small structure that hot electrons can occur in a plurality of first selected transistors, wherein a further transistor, a gate of which is connected to a fixed bias voltage, is connected between said first selected transistors and a plurality of second selected transistors connected to said poles of the feed voltage.
Claim 10
Dependent Claim
61 words
An integrated circuit according to claim 5, having such a small structure that hot electrons can occur in a plurality of first selected transistors, wherein a further transistor, a gate of which is connected to a fixed bias voltage, is connected between said first selected transistors and a plurality of second selected transistors connected to said poles of the feed voltage.
Claim 11
Dependent Claim
15 words
The integrated circuit arrangement of claim 2, wherein said differential amplifier is a read amplifier.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-04 | 1993-12-04 | 1994-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-04 | 1997-12-04 | 1998-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-04 | 2001-12-04 | 2002-06-05 | $7700.00 | Window Closed / Lapsed |