US4647797A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Assist circuit for improving the rise time of an electronic signal
Assignee: Intellectual Ventures I LLC
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Filing: 1984-08-23
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Granted: 1987-03-03
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Expires: 2004-08-23
Abstract
Abstract A circuit for improving the rise time of an electronic signal including a voltage generator for generating a reference voltage, a comparator for comparing the voltage of an electronic signal whose rise time is to be improved with the voltage of the reference voltage generator, and a current pulse generator controlled by the comparator for generating a current pulse of a predetermined duration responsive to the comparison of the comparator. The current pulse is of sufficient magnitude to assist the rise time of the electronic signal.
Inventors
- 👤 Ikuo J. Sanwo
- 👤 Albert P. Chiu
- 👤 William O. Kerber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:02
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
428 words
A circuit for decreasing the rise time of an electronic signal on a bus conductor, said circuit comprising: reference voltage means having an output for providing a reference voltage; comparator means having a first input connected to the output of said reference voltage means, a second input connected to the bus conductor and an output including a current source, said comparator means having an on state for conducting therethrough current from said current source when the electronic signal voltage on the bus conductor connected to its second input is lower than a set voltage related to the reference voltage on its first input, and a turned off condition for blocking current flow therethrough when the electronic signal voltage on the bus conductor connected to its second input rises to be equal to or exceeds the set voltage related to the reference voltage on its first input such that an enabling signal having a voltage at least equal to a set level will be provided on the output of said comparator means; time delay means comprising at least three inverter devices connected in series, said time delay means having an input connected to the output of said comparator means and an output whose output voltage will be changed to be at least equal to said set level about ten nanoseconds after its input has received the enabling signal from the output of said comparator means; a two state device having a first input connected to the output of said comparator means for receipt of the enabling signal, a second input connected to the output of said time delay means, and an output, the voltage on the output of said two state device having a first state when the voltages on both of the inputs of said two state device are at said set level, and a second state when either of the voltages on the inputs of said two state device is at a level different than said set level; and current providing means having an input connected to the output of said two state device and an output connected to the bus conductor, said current providing means having an on condition for providing current from its output to the bus conductor when the output voltage of said two state device is in its first state, and having an off condition when the output voltage of said two state device is in its second state, whereby the rise time of the electronic signal on the bus conductor is shortened when said current providing means is in its on condition.
Claim 2
Dependent Claim
428 words
A circuit for decreasing the rise time of an electronic signal on a bus conductor, said circuit comprising: reference voltage means having an output for providing a reference voltage; comparator means having a first input connected to the output of said reference voltage means, a second input connected to the bus conductor and an output including a current source, said comparator means having an on state for conducting therethrough current from said current source when the electronic signal voltage on the bus conductor connected to its second input is lower than a set voltage related to the reference voltage on its first input, and a turned off condition for blocking current flow therethrough when the electronic signal voltage on the bus conductor connected to its second input rises to be equal to or exceeds the set voltage related to the reference voltage on its first input such that an enabling signal having a voltage at least equal to a set level will be provided on the output of said comparator means; time delay means comprising at least three inverter devices connected in series, said time delay means having an input connected to the output of said comparator means and an output whose output voltage will be changed to be at least equal to said set level about ten nanoseconds after its input has received the enabling signal from the output of said comparator means; a two state device having a first input connected to the output of said comparator means for receipt of the enabling signal, a second input connected to the output of said time delay means, and an output, the voltage on the output of said two state device having a first state when the voltages on both of the inputs of said two state device are at said set level, and a second state when either of the voltages on the inputs of said two state device is at a level different than said set level; and current providing means having an input connected to the output of said two state device and an output connected to the bus conductor, said current providing means having an on condition for providing current from its output to the bus conductor when the output voltage of said two state device is in its first state, and having an off condition when the output voltage of said two state device is in its second state, whereby the rise time of the electronic signal on the bus conductor is shortened when said current providing means is in its on condition.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein said two-state device is a NAND gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-02 | 1990-09-01 | 1991-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-02 | 1994-09-01 | 1995-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-02 | 1998-09-01 | 1999-03-03 | $7700.00 | Window Closed / Lapsed |