US4621202A
Expired / Lapsed
US
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Bi-directional bus isolation circuit
Assignee: NXP USA Inc
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Filing: 1984-11-13
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Granted: 1986-11-04
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Expires: 2004-11-13
Abstract
Abstract A bi-directional bus isolation circuit couples the logic state present on a primary bus to a polysilicon secondary bus or the logic state present on the secondary bus to the primary bus in response to a select signal. A first NOR gate has one input coupled to the primary bus and a second input for receiving the select signal. A first output transistor couples the secondary bus to ground in response to the first NOR gate providing a logic high output. A second NOR gate has a first input coupled to the secondary bus, and a second input for receiving the select signal. A second output transistor couples the primary bus to ground in response to the second NOR gate providing a logic high output.
Inventors
- 👤 Joseph Pumo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:46
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C7/1048; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
115 words
A circuit, comprising: a primary bus; a secondary bus; a plurality of registers each having an output coupled to the secondary bus; a first logic gate having a first input coupled to the primary bus, a second input for receiving a select signal, and an output coupled to the secondary bus; a second logic gate having a first input coupled to the secondary bus, a second input for receiving the select signal, and an output coupled to the primary bus; and a first precharge transistor having a control electrode for receiving a clock signal, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the secondary bus.
Claim 2
Dependent Claim
115 words
A circuit, comprising: a primary bus; a secondary bus; a plurality of registers each having an output coupled to the secondary bus; a first logic gate having a first input coupled to the primary bus, a second input for receiving a select signal, and an output coupled to the secondary bus; a second logic gate having a first input coupled to the secondary bus, a second input for receiving the select signal, and an output coupled to the primary bus; and a first precharge transistor having a control electrode for receiving a clock signal, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the secondary bus.
Claim 3
Dependent Claim
74 words
The circuit of claim 1 wherein the first logic gate comprises: a first NOR gate having a first input coupled to the primary bus, a second input for receiving the select signal, and an output; and a first output transistor having a control electrode coupled to the output of the first NOR gate, a first current electrode coupled to the secondary bus, and a second current electrode coupled to a second power supply terminal.
Claim 4
Dependent Claim
19 words
The circuit of claim 3 wherein the first NOR gate has a third input for receiving the clock signal.
Claim 5
Dependent Claim
41 words
The circuit of claim 3 further comprising a second precharge transistor having a control electrode for receiving the clock signal, a first current electrode coupled to the first power supply terminal, and a second current electrode coupled to the primary bus.
Claim 6
Dependent Claim
74 words
The circuit of claim 4 wherein the second logic gate comprises: a second NOR gate having a first input coupled to the secondary bus, a second input for receiving the select signal, and an output; and a second output transistor having a control electrode coupled to the output of the second NOR gate, a first current electrode coupled to the primary bus, and a second current electrode coupled to the second power supply terminal.
Claim 7
Dependent Claim
19 words
The circuit of claim 5 wherein the second NOR gate has a third input for receiving the clock signal.
Claim 8
Dependent Claim
17 words
The circuit of claim 6 wherein the primary bus is metal and the secondary bus is polysilicon.
Claim 9
Dependent Claim
147 words
A bus isolation circuit coupled between a polysilicon secondary bus having a plurality of registers coupled thereto and a primary bus, comprising: a first NOR gate having a first input for receiving a select signal, a second input coupled to the primary bus, and an output; a first output transistor having a control electrode coupled to the output of the first NOR gate, a first current electrode coupled to the secondary bus, and a second current electrode coupled to a first power supply terminal; a second NOR gate having a first input for receiving the select signal, a second input coupled to the secondary bus, and an output; and a second output transistor having a control electrode coupled to the output of the second NOR gate, a first current electrode coupled to the primary bus, and a second current electrode coupled to the first power supply terminal.
Claim 10
Dependent Claim
147 words
A bus isolation circuit coupled between a polysilicon secondary bus having a plurality of registers coupled thereto and a primary bus, comprising: a first NOR gate having a first input for receiving a select signal, a second input coupled to the primary bus, and an output; a first output transistor having a control electrode coupled to the output of the first NOR gate, a first current electrode coupled to the secondary bus, and a second current electrode coupled to a first power supply terminal; a second NOR gate having a first input for receiving the select signal, a second input coupled to the secondary bus, and an output; and a second output transistor having a control electrode coupled to the output of the second NOR gate, a first current electrode coupled to the primary bus, and a second current electrode coupled to the first power supply terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-03 | 1990-05-05 | 1990-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-03 | 1994-05-05 | 1994-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-03 | 1998-05-05 | 1998-11-04 | $7700.00 | Window Closed / Lapsed |