US4926355A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital signal processor architecture with an ALU and a serial processing section operating in parallel
Assignee: General Datacomm Inc
•
Filing: 1987-07-02
•
Granted: 1990-05-15
•
Expires: 2007-07-02
Abstract
Abstract A digital signal processor (DSP) for conducting arithmetically complex functions, is provided. The DSP is preferably embodied as a single integrated circuit chip and generally includes a microinstruction sequencer (MIS) section, an arithmetic logic unit (ALU), a serial arithmetic processor section, a RAM section, and a system data bus. The MIS includes a coded ROM, a circuit for addressing the ROM, a ROM decoder for decoding the ROM code into control and data signals, and circuitry for sending the control and data signals to desired locations, and controls the functioning of the DSP. The ALU performs arithmetic and logic functions under the control of the ROM, while the serial arithmetic processor section conducts arithmetically complex functions under the control of the ROM. The RAM, under control of the ROM receives and stores data which is sent to the RAM via a system data bus directly from the ROM, from the ALU, from the serial arithmetic processor, and from circuitry exterior to the DSP. The RAM also sends via the data bus data to the ALU, the serial arithmetic processor, the microinstruction sequencer and the circuitry exterior to said digital signal processor under control of the ROM. The provided DSP is particularly advantageous in carrying out ADPCM algorithms.
Inventors
- 👤 Charles P. Boreland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:31
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
338 words
A digital signal processor, comprising: (a) a data bus; (b) a microinstruction sequencer means for controlling the functioning of the digital signal processor, including a coded ROM, means for addressing the ROM, means for decoding the ROM code into control and data signals, and means for sending the control and data signals to desired locations via said data bus; (c) arithmetic logic unit (ALU) means coupled to said data bus for performing arithmetic and logic functions under the control of said control signals; (d) an arithmetic processor section means coupled to said data bus for conducting under the control of said control signals arithmetically complex functions; and (e) a RAM means coupled to said data bus for receiving and storing data which is sent to the RAM means via said data bus under control of said control signals from at least one of said microinstruction sequencer, said ALU means, said arithmetic processor section means, and circuitry exterior to said digital signal processor, and for sending data via said data bus to at least one of said ALU means, said arithmetic processor section means, said microinstruction sequencer and said circuitry exterior to said digital signal processor under control of said control signals, wherein said data bus is written to and read by said arithmetic processor means, said ALU means, said microinstruction sequencer and said RAM means, said arithmetic processor section means and said ALU means function in parallel, said RAM means includes a RAM and a RAM data register coupled to said RAM for storing data output by said RAM and for storing data to be input into said RAM, said arithmetic-logic unit means includes an arithmetic-logic core and first and second ALU data registers coupled to said arithmetic-logic core for at least storing data which is to be processed by said ALU means, and said arithmetic processor section means includes a serial arithmetic processor and a serial arithmetic processor data register coupled to said serial arithmetic processor for storing data to be processed by said serial arithmetic processor.
Claim 2
Dependent Claim
338 words
A digital signal processor, comprising: (a) a data bus; (b) a microinstruction sequencer means for controlling the functioning of the digital signal processor, including a coded ROM, means for addressing the ROM, means for decoding the ROM code into control and data signals, and means for sending the control and data signals to desired locations via said data bus; (c) arithmetic logic unit (ALU) means coupled to said data bus for performing arithmetic and logic functions under the control of said control signals; (d) an arithmetic processor section means coupled to said data bus for conducting under the control of said control signals arithmetically complex functions; and (e) a RAM means coupled to said data bus for receiving and storing data which is sent to the RAM means via said data bus under control of said control signals from at least one of said microinstruction sequencer, said ALU means, said arithmetic processor section means, and circuitry exterior to said digital signal processor, and for sending data via said data bus to at least one of said ALU means, said arithmetic processor section means, said microinstruction sequencer and said circuitry exterior to said digital signal processor under control of said control signals, wherein said data bus is written to and read by said arithmetic processor means, said ALU means, said microinstruction sequencer and said RAM means, said arithmetic processor section means and said ALU means function in parallel, said RAM means includes a RAM and a RAM data register coupled to said RAM for storing data output by said RAM and for storing data to be input into said RAM, said arithmetic-logic unit means includes an arithmetic-logic core and first and second ALU data registers coupled to said arithmetic-logic core for at least storing data which is to be processed by said ALU means, and said arithmetic processor section means includes a serial arithmetic processor and a serial arithmetic processor data register coupled to said serial arithmetic processor for storing data to be processed by said serial arithmetic processor.
Claim 3
Dependent Claim
33 words
A digital signal processor according to claim 1, wherein: said RAM means further includes a bidirectional buffer, a controller, and an internal bus which connects said RAM, said controller and said bidirectional buffer.
Claim 4
Dependent Claim
111 words
A digital signal processor according to claim 1, wherein: said arithmetic processor section means is a serial arithmetic processor having converting means for converting an unsigned magnitude value received via said data bus into a logarithmic value, for converting a signed magnitude value received via said data bus into a floating point value, and for converting a logarithmic value received via said data bus into an unsigned value, and a multiplication means for multiplying two signed magnitude values received via said data bus, and for multiplying two floating point values received via said data bus to provide a product, wherein said converting means converts said product into a signed magnitude value.
Claim 5
Dependent Claim
43 words
A digital signal processor according to claim 1, wherein: said arithmetic logic unit means further includes a comparator for comparing the values in said first and second ALU data registers and for sending the result of said comparison to said microinstruction sequencer means.
Claim 6
Dependent Claim
41 words
A digital signal processor according to claim 4, wherein: said microinstruction sequencer means includes means for instructing said arithmetic logic unit means to conduct a conditional operation on data in at least one of said first and second ALU data registers.
Claim 7
Dependent Claim
41 words
A digital signal processor according to claim 5, wherein: said means for instructing said ALU means to conduct a conditional operation uses the result of said comparison made by said comparator in determining the conditional operation said ALU is to conduct.
Claim 8
Dependent Claim
111 words
A digital signal processor according to claim 6, wherein: said arithmetic processor section means is a serial arithmetic processor having converting means for converting an unsigned magnitude value received via said data bus into a logarithmic value, for converting a signed magnitude value received via said data bus into a floating point value, and for converting a logarithmic value received via said data bus into an unsigned value, and a multiplication means for multiplying two signed magnitude values received via said data bus, and for multiplying two floating point values received via said data bus to provide a product, wherein said converting means converts said product into a signed magnitude value.
Claim 9
Dependent Claim
87 words
A digital signal processor according to claim 7, where said digital signal processor receives data from input/output circuitry coupled to said digital signal processor, wherein: said microinstruction sequencer is programmed with a plurality of microinstructions which control said digital signal processor and cause said data received by said digital signal processor from said input/output circuitry to be encoded and decoded according to an ADPCM algorithm, such that in encoding and decoding said data, said data is processed by said ALU means and said arithmetic processor section means.
References Cited (Backward Citations)
US3694642A
Cited
US3768077A
Cited
US3840861A
Cited
US4079447A
Cited
US3930232A
Cited
US4041461A
Cited
US4258429A
Cited
US4156927A
Cited
US4209836A
Cited
US4365312A
Cited
US4272808A
Cited
US4367524A
Cited
US4467444A
Cited
US4393468A
Cited
US4542476A
Cited
US4615004A
Cited
US4450525A
Cited
US4551841A
Cited
US4639886A
Cited
US4649508A
Cited
US4520347A
Cited
US4608660A
Cited
US4574348A
Cited
EP0171190A2
Cited
US4785393A
Cited
US4622680A
Cited
US4700319A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |