US3768077A
Expired / Lapsed
US
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Data processor with reflect capability for shift operations
Assignee: International Business Machines Corp
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Filing: 1972-04-24
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Granted: 1973-10-23
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Expires: 1992-04-24
Abstract
Abstract A data processor is described in which general purpose registers having a unidirectional shift capability are employed in conjunction with a reflect operation to effectively execute multiply or divide operations. The outputs of a register having unidirectional shift capability are presented to one set of inputs on an input multiplexor of an arithmetic logic unit (ALU) in normal bit order for operations requiring no shift or a right shift. They are also presented to a second set of inputs on the input multiplexor of the ALU in bit reversed order to provide a reflect capability in data flow from the register, through the ALU, and back to the input of the register.
Inventors
- 👤 R Nier
- 👤 D Waldecker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:00
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G06F5/00; G06F5/01
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
143 words
In a data processor, apparatus for executing multiply and divide operations, comprising: a shift register having the capability of shifting data to the right; an arithmetic logic unit for performing multiply and divide iterations; first means for gating outputs of said register to said arithmetic logic unit in bit reversed order such that the high order bit of said register appears at the low order bit position of said arithmetic logic unit and a low order bit from said register appears as a high order bit position in said arithmetic logic unit; second means for gating outputs of said register to inputs of said arithmetic logic unit in correct bit order; microprogram control means for controlling the operation of said first and second gating means; and means for generating arithmetic result bits in response to iterative steps executed by said arithmetic logic unit.
Claim 2
Dependent Claim
143 words
In a data processor, apparatus for executing multiply and divide operations, comprising: a shift register having the capability of shifting data to the right; an arithmetic logic unit for performing multiply and divide iterations; first means for gating outputs of said register to said arithmetic logic unit in bit reversed order such that the high order bit of said register appears at the low order bit position of said arithmetic logic unit and a low order bit from said register appears as a high order bit position in said arithmetic logic unit; second means for gating outputs of said register to inputs of said arithmetic logic unit in correct bit order; microprogram control means for controlling the operation of said first and second gating means; and means for generating arithmetic result bits in response to iterative steps executed by said arithmetic logic unit.
Claim 3
Dependent Claim
125 words
Apparatus for executing logic operations in a data processor, comprising: an arithmetic logic unit having a plurality of inputs and outputs; an input multiplexor having a plurality of sets of inputs and having an output connected to a first set of inputs of said arithmetic logic units; a unidirectional shift register having a plurality of stages, each stage having an output connected to one of a first set of inputs of said input multiplexor in a first bit order and being connected to a second set of inputs of said input multiplexor in a second bit order reversed from said first bit order; and control means for generating a plurality of control signals for controlling the execution of logic operations in said arithmetic logic unit.
Claim 4
Dependent Claim
125 words
Apparatus for executing logic operations in a data processor, comprising: an arithmetic logic unit having a plurality of inputs and outputs; an input multiplexor having a plurality of sets of inputs and having an output connected to a first set of inputs of said arithmetic logic units; a unidirectional shift register having a plurality of stages, each stage having an output connected to one of a first set of inputs of said input multiplexor in a first bit order and being connected to a second set of inputs of said input multiplexor in a second bit order reversed from said first bit order; and control means for generating a plurality of control signals for controlling the execution of logic operations in said arithmetic logic unit.
Claim 5
Dependent Claim
238 words
Apparatus for executing logic operations in a data processor, comprising: an arithmetic logic unit having a plurality of inputs and an output; an input multiplexor having a plurality of sets of inputs and having an output connected to a first set of inputs of said arithmetic logic unit; an output multiplexor having an input connected to said output of said arithmetic logic unit, said output multiplexor having a first set of outputs representing data output of said arithmetic logic unit and a second output representing sign of said data; a unidirectional shift register having a plurality of stages, each stage having an output connected to one of a first set of inputs of said input multiplexor in a first bit order and being connected to a second set of inputs of said input multiplexor in a second bit order reversed from said first bit order; control means for generating a plurality of control signals for controlling the execution of logical operations in said arithmetic logic unit, said plurality of control signals including a first control signal for controlling said first set of inputs to said input multiplexor and a second control signal for controlling said second set of inputs to said input multiplexor so that data from said unidirectional shift register may be gated to said ALU in either said first bit order or in said second bit reversed order as required by the logical operation being executed.
Claim 6
Dependent Claim
238 words
Apparatus for executing logic operations in a data processor, comprising: an arithmetic logic unit having a plurality of inputs and an output; an input multiplexor having a plurality of sets of inputs and having an output connected to a first set of inputs of said arithmetic logic unit; an output multiplexor having an input connected to said output of said arithmetic logic unit, said output multiplexor having a first set of outputs representing data output of said arithmetic logic unit and a second output representing sign of said data; a unidirectional shift register having a plurality of stages, each stage having an output connected to one of a first set of inputs of said input multiplexor in a first bit order and being connected to a second set of inputs of said input multiplexor in a second bit order reversed from said first bit order; control means for generating a plurality of control signals for controlling the execution of logical operations in said arithmetic logic unit, said plurality of control signals including a first control signal for controlling said first set of inputs to said input multiplexor and a second control signal for controlling said second set of inputs to said input multiplexor so that data from said unidirectional shift register may be gated to said ALU in either said first bit order or in said second bit reversed order as required by the logical operation being executed.
Claim 7
Independent Claim
128 words
A method of executing logical operations in a data processor, comprising the steps of: loading an operand into a first register; determining from a logical operation to be executed the direction of shifting required to place a result of said logical operation into said register; reflecting said operand from said register through an arithmetic logic unit to said register in bit reversed order for those logical operations requiring a shift in a first direction; executing said logical operation iteratively in said arithmetic logic unit including the step of shifting a result into said register; and reflecting said result from said register through said arithmetic logic unit to said register to place said result in correct bit order for those logical operations requiring a shift in said first direction.
Claim 8
Independent Claim
128 words
A method of executing logical operations in a data processor, comprising the steps of: loading an operand into a first register; determining from a logical operation to be executed the direction of shifting required to place a result of said logical operation into said register; reflecting said operand from said register through an arithmetic logic unit to said register in bit reversed order for those logical operations requiring a shift in a first direction; executing said logical operation iteratively in said arithmetic logic unit including the step of shifting a result into said register; and reflecting said result from said register through said arithmetic logic unit to said register to place said result in correct bit order for those logical operations requiring a shift in said first direction.
Claim 9
Independent Claim
119 words
A method of executing a divide operation in a data processor having a quotient register capable of shifting only to the right, comprising the steps of: loading a dividend into said register; identifying the operation to be executed as a divide operation; reflecting said dividend from said register through an arithmetic logic unit to said register in bit reversed order; executing a divide iteration on said dividend; shifting a quotient bit resulting from said divide iteration to a high order bit position of said register; repeating said steps of executing and shifting iteratively n times for an n bit quotient; and reflecting said bit reversed order quotient through said arithmetic logic unit to said register in corrected bit order.
Claim 10
Independent Claim
119 words
A method of executing a divide operation in a data processor having a quotient register capable of shifting only to the right, comprising the steps of: loading a dividend into said register; identifying the operation to be executed as a divide operation; reflecting said dividend from said register through an arithmetic logic unit to said register in bit reversed order; executing a divide iteration on said dividend; shifting a quotient bit resulting from said divide iteration to a high order bit position of said register; repeating said steps of executing and shifting iteratively n times for an n bit quotient; and reflecting said bit reversed order quotient through said arithmetic logic unit to said register in corrected bit order.
References Cited (Backward Citations)
US3400371A
Cited
US3510846A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-22 | 1977-04-23 | 1977-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-22 | 1981-04-23 | 1981-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-22 | 1985-04-23 | 1985-10-23 | $7700.00 | Window Closed / Lapsed |