Method and apparatus for non-intrusive bit error rate testing

Claim 1

A method of measuring a bit error rate of a data stream in a digital communications circuit comprising the steps of: repeatedly intermittently sampling data bits in the data stream according to a sampling algorithm at upstream and downstream monitor points to produce upstream and downstream sets of sampled data bits; dividing the upstream set of sampled data bits into upstream blocks of predetermined block size; computing upstream block check codes on the upstream blocks; dividing the downstream set of sampled data bits into downstream blocks of predetermined block size; computing downstream block check codes on the downstream blocks; synchronizing the sampling of the data bits at the upstream and downstream monitor points, the dividing of the upstream and downstream sets of sampled data bits into the upstream and downstream blocks, and the computing of the upstream and downstream block check codes in order to ensure that the upstream block check codes are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed; comparing the upstream block check codes that are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed and the downstream block check codes with each other to determine a number of miscompares; and determing a bit error rate or a quantity representative thereof based on the number of miscompares.

Claim 2

A method of measuring a bit error rate of a data stream in a digital communications circuit comprising the steps of: repeatedly intermittently sampling data bits in the data stream according to a sampling algorithm at upstream and downstream monitor points to produce upstream and downstream sets of sampled data bits; dividing the upstream set of sampled data bits into upstream blocks of predetermined block size; computing upstream block check codes on the upstream blocks; dividing the downstream set of sampled data bits into downstream blocks of predetermined block size; computing downstream block check codes on the downstream blocks; synchronizing the sampling of the data bits at the upstream and downstream monitor points, the dividing of the upstream and downstream sets of sampled data bits into the upstream and downstream blocks, and the computing of the upstream and downstream block check codes in order to ensure that the upstream block check codes are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed; comparing the upstream block check codes that are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed and the downstream block check codes with each other to determine a number of miscompares; and determing a bit error rate or a quantity representative thereof based on the number of miscompares.

Claim 7

A system for measuring a bit error rate of a data stream in a digital communications circuit comprising: means for repeatedly intermittently sampling data bits in the data stream according to a sampling algorithm at upstream and downstream mointor points to produce upstream and downstream sets of sampled data bits; means for dividing the upstream set of sampled data bits into upstream blocks of predetermined block size; means for computing upstream block check codes on the upstream blocks; means for dividing the downstream set of sampled data bits into downstream blocks of predetermined block size; means for computing downstream block check codes on the downstream blocks; means for synchronizing the sampling of the data bits at the upstream and downstream monitor points, the dividing of the upstream and downstream sets of sampled data bits into the upstream and downstream blocks, and the computing of the upstream and downstream block check codes in order to ensure that the upstream block check codes are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed; comparison means for comparing the upstream block check codes that are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed and the downstream block check codes with each other to determined a number of miscompares; and determining means for determining a bit error rate or a quantity representative thereof based on the number of miscompares.

Claim 8

A system for measuring a bit error rate of a data stream in a digital communications circuit comprising: means for repeatedly intermittently sampling data bits in the data stream according to a sampling algorithm at upstream and downstream mointor points to produce upstream and downstream sets of sampled data bits; means for dividing the upstream set of sampled data bits into upstream blocks of predetermined block size; means for computing upstream block check codes on the upstream blocks; means for dividing the downstream set of sampled data bits into downstream blocks of predetermined block size; means for computing downstream block check codes on the downstream blocks; means for synchronizing the sampling of the data bits at the upstream and downstream monitor points, the dividing of the upstream and downstream sets of sampled data bits into the upstream and downstream blocks, and the computing of the upstream and downstream block check codes in order to ensure that the upstream block check codes are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed; comparison means for comparing the upstream block check codes that are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed and the downstream block check codes with each other to determined a number of miscompares; and determining means for determining a bit error rate or a quantity representative thereof based on the number of miscompares.

Claim 13

A method of measuring a bit error rate of a data stream in a digital communications circuit comprising the steps of: repeatedly intermittently sampling data bits in the data stream according to a plurality of sampling algorithms at upstream and downstream monitor points to produce a plurality of upstream sets of sampled data bits and a plurality of downstream sets of sampled data bits such that each of the plurality of upstream sets of sampled data bits corresponds to one of the plurality of downstream sets of sampled data bits; dividing each of the plurality of upstream sets of sampled data bits into upstream blocks having a predetermined block size such that the predetermined block size for any one of the plurality of upstream sets of sampled data bits differs from the predetermined block size for any other of the plurality of upstream sets of sampled data bits; computing upstream block check codes on the upstream blocks for each of the plurality of upstream sets of sampled data bits; dividing each of the plurality of downstream sets of sampled data bits into downstream blocks having a predetermined block size such that the predetermined block size for any one of the plurality of downstream sets of sampled data bits differs from the predetermined block size for any other of the plurality of downstream sets of sampled data bits; computing downstream block check codes on the downstream blocks for each of the plurality of downstream sets of sampled data bits; synchronizing the sampling of the data bits at the upstream and downstream monitor points, the dividing of the upstream and downstream sets of sampled data bits into the upstream and downstream blocks, and the computing of the upstream and downstream block check codes in order to ensure that for each of the plurality of upstream sets of sampled data bits and its one corresponding downstream set of sampled data bits, the upstream block check codes are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed; comparing the upstream block check codes for each of the plurality of upstream sets of sampled data bits with the downstream block check codes for the corresponding downstream set of sampled data bits to determine a number of miscompares for each of the plurality of upstream sets of sampled data bits and its one corresponding downstream set of sampled data bits; determining a selection criteria; selecting one of the plurality of upstream sets of samped data bits and its one corresponding downstream set of sampled data bits based on the selection criteria; and determining a bit error rate or a quantity representative thereof based on the determined number of miscompares for the one selected upstream set of sampled data bits and its corresponding downstream set of sampled data bits.

Claim 14

A method of measuring a bit error rate of a data stream in a digital communications circuit comprising the steps of: repeatedly intermittently sampling data bits in the data stream according to a plurality of sampling algorithms at upstream and downstream monitor points to produce a plurality of upstream sets of sampled data bits and a plurality of downstream sets of sampled data bits such that each of the plurality of upstream sets of sampled data bits corresponds to one of the plurality of downstream sets of sampled data bits; dividing each of the plurality of upstream sets of sampled data bits into upstream blocks having a predetermined block size such that the predetermined block size for any one of the plurality of upstream sets of sampled data bits differs from the predetermined block size for any other of the plurality of upstream sets of sampled data bits; computing upstream block check codes on the upstream blocks for each of the plurality of upstream sets of sampled data bits; dividing each of the plurality of downstream sets of sampled data bits into downstream blocks having a predetermined block size such that the predetermined block size for any one of the plurality of downstream sets of sampled data bits differs from the predetermined block size for any other of the plurality of downstream sets of sampled data bits; computing downstream block check codes on the downstream blocks for each of the plurality of downstream sets of sampled data bits; synchronizing the sampling of the data bits at the upstream and downstream monitor points, the dividing of the upstream and downstream sets of sampled data bits into the upstream and downstream blocks, and the computing of the upstream and downstream block check codes in order to ensure that for each of the plurality of upstream sets of sampled data bits and its one corresponding downstream set of sampled data bits, the upstream block check codes are computed on the upstream blocks that are made up of the data bits that represent the same positions in the data stream as the data bits that make up the downstream blocks on which the downstream block check codes are computed; comparing the upstream block check codes for each of the plurality of upstream sets of sampled data bits with the downstream block check codes for the corresponding downstream set of sampled data bits to determine a number of miscompares for each of the plurality of upstream sets of sampled data bits and its one corresponding downstream set of sampled data bits; determining a selection criteria; selecting one of the plurality of upstream sets of samped data bits and its one corresponding downstream set of sampled data bits based on the selection criteria; and determining a bit error rate or a quantity representative thereof based on the determined number of miscompares for the one selected upstream set of sampled data bits and its corresponding downstream set of sampled data bits.