US4234954A
Expired / Lapsed
US
⏱️ 0.0 years remaining
On-line bit error rate estimator
Assignee: Lockheed Martin Corp
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Filing: 1979-01-24
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Granted: 1980-11-18
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Expires: 1999-01-24
Abstract
Abstract This on-line circuit estimates the bit error rate (BER) of a binary data signal stream in the presence of noise uncorrelated with the signal. For a binary data signal having two states, e.g., plus V and minus V biased around a specified reference level (REF), the circuit counts the number of instances in which the received signal deviates more than 2V from the reference level. This accumulated count gives an accurate estimate of the BER over several orders of magnitude variation of the BER. One embodiment counts just the deviations in a positive direction. This circuit functions independently of any bit pattern and can be used for on-line monitoring without decreasing the information carrying capability of the link. The time required to accumulate a statistically significant sample is the same as for a direct comparison between sent and received bits.
Inventors
- 👤 Julius Lange
- 👤 Gary L. Wagner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:54
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
101 words
Apparatus for detecting the rate of error in an input binary coded data stream not including code characters of the parity check type, said apparatus comprising: means for generating a relative test voltage equal to approximately twice the average relative signal voltage of the data stream; and means connected to said generating means for producing an error pulse only whenever, at any one of many preselected sampling points clocked onto said producing means by clocking means connected thereto, the magnitude of the relative voltage of the data stream, including any noise superimposed thereon, exceeds the magnitude of said relative test voltage.
Claim 2
Dependent Claim
101 words
Apparatus for detecting the rate of error in an input binary coded data stream not including code characters of the parity check type, said apparatus comprising: means for generating a relative test voltage equal to approximately twice the average relative signal voltage of the data stream; and means connected to said generating means for producing an error pulse only whenever, at any one of many preselected sampling points clocked onto said producing means by clocking means connected thereto, the magnitude of the relative voltage of the data stream, including any noise superimposed thereon, exceeds the magnitude of said relative test voltage.
Claim 3
Dependent Claim
43 words
The apparatus of claim 1 wherein said clocking means establishes a series of sampling intervals of uniform duration equal to the average interval between pulses of the input data stream, with each said sampling point occurring at the end of a sampling interval.
Claim 4
Dependent Claim
36 words
The apparatus of claim 1 wherein the relative test voltage is positive and error pulses are produced only when the relative voltage of the data stream, including any noise superimposed thereon, exceeds said relative test voltage.
Claim 5
Dependent Claim
52 words
The apparatus of claim 1 further comprising an automatic gain control circuit (a.g.c.) connected to said generating means and to said input data stream, said a.g.c. setting two reference relative voltages, equal to the average relative maximum and the average relative minimum of the data stream voltage at the sampling points, respectively.
Claim 6
Dependent Claim
78 words
The apparatus of claim 4 wherein said automatic gain control circuit comprises two comparators, each having an inverting input terminal, a non-inverting input terminal and an output; a first decision flip-flop whose input is connected via a wired OR-gate to the outputs of each of said comparators; an operational amplifier whose non-reference input terminal is connected to the output terminal of said first flip-flop; and at least one voltage divider connected to the output of said operational amplifier.
Claim 7
Dependent Claim
87 words
The apparatus of claim 5 further comprising a lowpass filter connected between the output terminal of said first flip-flop and the non-reference input terminal of said operational amplifier; a unity gain inverting amplifier whose input is connected to the output of said operational amplifier; a first voltage divider connected between the output terminal of said operational amplifier and the non-inverting terminal of said first comparator; and a second voltage divider connected between the output terminal of said inverting amplifier and the inverting terminal of said second comparator.
Claim 8
Dependent Claim
41 words
The apparatus of claim 6 wherein said means for generating a relative test voltage comprises a power supply whose input is connected to the output of said inverting amplifier and whose output is connected to said means for producing error pulses.
Claim 9
Dependent Claim
17 words
The apparatus of claim 1 wherein said means for producing error pulses comprises a second decision flip-flop.
Claim 10
Independent Claim
307 words
An apparatus for estimating the binary error rate on an input data stream of binary signals whose average maximum voltage, representing a binary "one," is R+V, and whose average minimum voltage, representing a binary "zero," is R-V, comprising: a servo loop for establishing values of R-V and R+V, respectively, including a first and second comparator, the input data stream being connected to the inverting terminal of said first comparator and to the non-inverting terminal of said second comparator; a first decision flip-flop whose input is connected via a wired OR-gate to the outputs of each of said two comparators; a lowpass filter whose input is connected to the output of said first flip-flop; an operational amplifier whose non-reference input terminal is connected to the output of said lowpass filter and whose reference terminal is connected via a second lowpass filter to a point which is at voltage R; a unity gain inverting amplifier whose input is connected to the output of said operational amplifier; a first voltage divider which is connected between the output of said operational amplifier and the non-inverting terminal of said first comparator; a second voltage divider which is connected between the reference terminal of said unity gain inverting amplifier and the inverting terminal of said second comparator; a power supply whose input is connected to the output of said unity gain inverting amplifier and which removes the value R from the voltage at said terminal; a second decision flip-flop, one power supply input terminal of which is connected to the output of said power supply and the data input terminal of which is connected to the input data stream; wherein a clock input pulse set at approximately the same rate as the data rate of the input data stream is connected to the clock terminals of each of said first and second flip-flops.
Claim 11
Independent Claim
307 words
An apparatus for estimating the binary error rate on an input data stream of binary signals whose average maximum voltage, representing a binary "one," is R+V, and whose average minimum voltage, representing a binary "zero," is R-V, comprising: a servo loop for establishing values of R-V and R+V, respectively, including a first and second comparator, the input data stream being connected to the inverting terminal of said first comparator and to the non-inverting terminal of said second comparator; a first decision flip-flop whose input is connected via a wired OR-gate to the outputs of each of said two comparators; a lowpass filter whose input is connected to the output of said first flip-flop; an operational amplifier whose non-reference input terminal is connected to the output of said lowpass filter and whose reference terminal is connected via a second lowpass filter to a point which is at voltage R; a unity gain inverting amplifier whose input is connected to the output of said operational amplifier; a first voltage divider which is connected between the output of said operational amplifier and the non-inverting terminal of said first comparator; a second voltage divider which is connected between the reference terminal of said unity gain inverting amplifier and the inverting terminal of said second comparator; a power supply whose input is connected to the output of said unity gain inverting amplifier and which removes the value R from the voltage at said terminal; a second decision flip-flop, one power supply input terminal of which is connected to the output of said power supply and the data input terminal of which is connected to the input data stream; wherein a clock input pulse set at approximately the same rate as the data rate of the input data stream is connected to the clock terminals of each of said first and second flip-flops.
Claim 12
Independent Claim
77 words
A method for estimating the binary error rate of a binary coded data stream not including code characters of the parity check type, said method comprising: establishing from the data stream itself the average maximum voltage deviation with respect to the normal baseline voltage of the input data stream; doubling this average deviation to obtain a reference deviation; and comparing the voltage deviation of the input data stream to this reference deviation at many predetermined sampling points.
Claim 13
Independent Claim
77 words
A method for estimating the binary error rate of a binary coded data stream not including code characters of the parity check type, said method comprising: establishing from the data stream itself the average maximum voltage deviation with respect to the normal baseline voltage of the input data stream; doubling this average deviation to obtain a reference deviation; and comparing the voltage deviation of the input data stream to this reference deviation at many predetermined sampling points.
Claim 14
Dependent Claim
27 words
The method of claim 10 wherein said comparing step produces an error pulse each time said data stream deviation exceeds said reference deviation at a sampling point.
Claim 15
Dependent Claim
33 words
The method of claim 10 wherein the intervals between sampling points are determined by a clock whose frequency is set at the same rate as the bit rate of the input data stream.
Claim 16
Dependent Claim
17 words
The method of claim 10 wherein said establishing step is performed by an automatic gain control circuit.
Claim 17
Dependent Claim
14 words
The method of claim 10 wherein said comparing is performed by a decision flip-flop.
Claim 18
Dependent Claim
27 words
The method of claim 10 further comprising the step of regenerating a clean output data stream from the input data stream for output to a digital recipient.
Claim 19
Dependent Claim
11 words
The method of claim 10 wherein said deviations are all positive.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-18 | 1984-05-19 | 1984-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-18 | 1988-05-19 | 1988-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-18 | 1992-05-19 | 1992-11-18 | $7700.00 | Window Closed / Lapsed |