US4800562A — Circuit and method for monitoring the quality of …

Claim 1

Independent Claim 139 words

An event ratio detector circuit comprising a first counter means having a predetermined maximum count and being responsive to each event of a first sequence of events for increasing its count by one, and a second counter means having a predetermined maximum count and being responsive to each event of a second sequence of events for increasing its count by one, the overflow output of the first counter means being connected to the clear input of the second counter means, and the overflow output of the second counter means being connected to the clear input of the first counter means, a signal appearing at the overflow output of the second counter means indicating that the ratio of second events to first events as predetermined by the respective maximum counts of the second and first counter means has been exceeded.

Claim 2

Dependent Claim 139 words

An event ratio detector circuit comprising a first counter means having a predetermined maximum count and being responsive to each event of a first sequence of events for increasing its count by one, and a second counter means having a predetermined maximum count and being responsive to each event of a second sequence of events for increasing its count by one, the overflow output of the first counter means being connected to the clear input of the second counter means, and the overflow output of the second counter means being connected to the clear input of the first counter means, a signal appearing at the overflow output of the second counter means indicating that the ratio of second events to first events as predetermined by the respective maximum counts of the second and first counter means has been exceeded.

Claim 3

Dependent Claim 60 words

A circuit as defined in claim 1 and further comprising a flip-flop having its set input connected to the overflow output of the second counter means and its reset input connected to the overflow output of the first counter means, whereby a signal at the Q output of the flip-flop indicates whether or not said predetermined ratio has been exceeded.

Claim 4

Dependent Claim 179 words

In a receiver circuit adapted to receive a digital data stream on a transmission link, the receiver circuit comprising a signal generator adapted to provide a periodic bit corresponding to each one of predetermined occurrences in the data stream, an error detector circuit adapted to provide an error bit corresponding to each error of predetermined type detected in the received data and a source of clock pulses synchronized to the bits of the data stream, a circuit for monitoring the performance of the transmission link comprising: a first counter means having a predetermined maximum count and being responsive to each of the periodic bits and a clock pulse for increasing its count by one, a second counter means having a predetermined maximum count and being responsive to each error bit and a clock pulse for increasing its count by one, the overflow output of the first counter means being connected to the clear input of the first counter means, a signal appearing at said overflow output of the second counter means representing a flag signal to the receiver circuit.

Claim 5

Dependent Claim 179 words

In a receiver circuit adapted to receive a digital data stream on a transmission link, the receiver circuit comprising a signal generator adapted to provide a periodic bit corresponding to each one of predetermined occurrences in the data stream, an error detector circuit adapted to provide an error bit corresponding to each error of predetermined type detected in the received data and a source of clock pulses synchronized to the bits of the data stream, a circuit for monitoring the performance of the transmission link comprising: a first counter means having a predetermined maximum count and being responsive to each of the periodic bits and a clock pulse for increasing its count by one, a second counter means having a predetermined maximum count and being responsive to each error bit and a clock pulse for increasing its count by one, the overflow output of the first counter means being connected to the clear input of the first counter means, a signal appearing at said overflow output of the second counter means representing a flag signal to the receiver circuit.

Claim 6

Dependent Claim 61 words

A circuit as defined in claim 3 and further comprising a flip-flop having its set input connected to the overflow output of the second counter means and its reset input connected to the overflow output of the first counter means whereby a signal at the Q output of the flip-flop indicates that the transmission link does not meet its performance criteria.

Claim 7

Dependent Claim 27 words

A circuit as defined in claim 4 wherein the predetermined maximum count of the first counter means is substantially greater than that of the second counter means.

Claim 8

Independent Claim 150 words

A method of monitoring the performance of a digital transmission system comprising the steps of: defining periods during each of which a plurality of errors may occur and for each such period, incrementing the value of a first counter means having a predetermined maximum count, in respect of each period of the first counter means, incrementing the value of a second counter means having a predetermined maximum count by one count if at least one error has occurred therein, causing the second counter means to be reset when the first counter means reaches its maximum count and thus resetting itself, and generating an output signal at the output of the second counter means when it reaches its maximum count and thus resetting itself, the output signal being effective for resetting the first counter means, the output signal being indicative that the performance criteria of the transmission system are not met.

Claim 9

Independent Claim 150 words

A method of monitoring the performance of a digital transmission system comprising the steps of: defining periods during each of which a plurality of errors may occur and for each such period, incrementing the value of a first counter means having a predetermined maximum count, in respect of each period of the first counter means, incrementing the value of a second counter means having a predetermined maximum count by one count if at least one error has occurred therein, causing the second counter means to be reset when the first counter means reaches its maximum count and thus resetting itself, and generating an output signal at the output of the second counter means when it reaches its maximum count and thus resetting itself, the output signal being effective for resetting the first counter means, the output signal being indicative that the performance criteria of the transmission system are not met.

Claim 10

Dependent Claim 26 words

A method as defined in claim 6 wherein the predetermined maximum count of the first counter means is greater than that of the second counter means.

Claim 11

Dependent Claim 35 words

A method as defined in claim 7 and further comprising the step of setting a flag in response to the output signal, whereby an alarm signal may be generated for use by data receiving circuitry.

Claim 12

Dependent Claim 26 words

A method as defined in claim 8 and comprising the further step of resetting said flag when the first counter means reaches its predetermined maximum count.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1992-01-24	1992-07-25	1993-01-24	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1996-01-24	1996-07-25	1997-01-24	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2000-01-24	2000-07-25	2001-01-24	$7700.00	Window Closed / Lapsed

Circuit and method for monitoring the quality of data in a data stream

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