Error detector for pseudo-random sequence of digits

Claim 2

In an error detector for a pseudo-random sequence of digits comprising: means responsive to said sequence of digits for generating a replicated sequence of digits; and means for comparing corresponding digits of the replicated sequence with those of said pseudo-random sequence to derive indicated error digits when anticoincidence is detected between said sequences; the improvement comprising: means responsive to true error digits for generating replicated error digits; and means for comparing said indicated error digits with said replicated error digits to derive said true error digits when anticoincidence is detected between said indicated and replicated error digits.

Claim 3

An error detector as defined in claim 1 in which the improvement additionally comprises: means for counting said true error digits to derive a signal for resetting the means for generating replicated error digits, said counting means being reset by said indicated error digits so as to re-establish a true error count after loss of synchronization.

Claim 4

An error detector, for detecting errors in a digital transmission system including a pseudo-random sequence generator for transmitting 2n-1 sequence of pseudo-random binary digits where n is a natural number, the error detector comprising: first and second n-stage shift registers, first and second modulo-2 adders connected in like combination to selected stages of the first and second n-stage shift registers respectively to replicate at the outputs of said adders the binary inputs to said shift registers; a third modulo-2 adder having one input connected to the output of the first modulo-2 adder; means for connecting said sequence of binary digits, from said pseudo-random sequence generator transmitted via said digital transmission system, to the input of the first n-stage shift register and to the other input of the third modulo-2 adder to derive at the latter''s output indicated error digits at effectively triple the true error rate; a fourth modulo-2 adder having one input connected to the output of the third modulo-2 adder, the other input connected to the output of the second modulo-2 adder, and its output connected to the input of the second n-stage shift register to derive from its said output true error digits.

Claim 5

An error detector, for detecting errors in a digital transmission system including a pseudo-random sequence generator for transmitting 2n-1 sequence of pseudo-random binary digits where n is a natural number, the error detector comprising: first and second n-stage shift registers, first and second modulo-2 adders connected in like combination to selected stages of the first and second n-stage shift registers respectively to replicate at the outputs of said adders the binary inputs to said shift registers; a third modulo-2 adder having one input connected to the output of the first modulo-2 adder; means for connecting said sequence of binary digits, from said pseudo-random sequence generator transmitted via said digital transmission system, to the input of the first n-stage shift register and to the other input of the third modulo-2 adder to derive at the latter''s output indicated error digits at effectively triple the true error rate; a fourth modulo-2 adder having one input connected to the output of the third modulo-2 adder, the other input connected to the output of the second modulo-2 adder, and its output connected to the input of the second n-stage shift register to derive from its said output true error digits.

Claim 6

An error detector as defined in claim 3 which additionally comprises a counter of about 2n digits having its input connected to the output of the fourth modulo-2 adder, the counter including a reset means connected to the output of the third modulo-2 adder; and the second n-stage shift register including a reset means connected to the output of the counter so as to re-establish a true error count after loss of synchronization with the sequence of pseudo-random binary digits.

Claim 7

A corrector, for an error detector including a comparator for comparing a pseudo-random sequence of digits against a replicated sequence of digits to derive indicated error digits during anticoincidence between the sequences; the corrector comprising: means responsive to true error digits for generating replicated error digits; and means for comparing said indicated error digits with said replicated error digits to derive said true error digits when anticoincidence is detected between said indicated and replicated error digits.

Claim 8

A corrector, for an error detector including a comparator for comparing a pseudo-random sequence of digits against a replicated sequence of digits to derive indicated error digits during anticoincidence between the sequences; the corrector comprising: means responsive to true error digits for generating replicated error digits; and means for comparing said indicated error digits with said replicated error digits to derive said true error digits when anticoincidence is detected between said indicated and replicated error digits.

Claim 9

An arrangement as defined in claim 5 additionally comprIsing: a counter for resetting the corrector when the true error digits exceed the indicated error digits by a preselected number.

Claim 10

An error detector for a pseudo-random sequence of binary digits comprising: a comparator including a first n-stage shift register, a first modulo-2 adder connected to selected stages of said first n-stage shift register to replicate at the output of said first modulo-2 adder the binary input to said first n-stage shift register, a second modulo-2 adder having one input connected to the output of the first modulo-2 adder; and means for connecting the pseudo-random sequence of binary digits to said first n-stage shift register and to the other input of the second modulo-2 adder to derive at the latter''s output indicated error digits at effectively triple the true error rate; a corrector including a second n-stage shift register, a third modulo-2 adder connected to selected stages of said second n-stage shift register to replicate at the output of said third modulo-2 adder the binary input to said second n-stage shift register; a fourth modulo-2 adder having one input connected to the output of the second modulo-2 adder and the other input connected to the output of the third modulo-2 adder to derive at its output true error digits, the fourth modulo-2 adder being connected to the input of the second n-stage shift register.

Claim 11

An error detector for a pseudo-random sequence of binary digits comprising: a comparator including a first n-stage shift register, a first modulo-2 adder connected to selected stages of said first n-stage shift register to replicate at the output of said first modulo-2 adder the binary input to said first n-stage shift register, a second modulo-2 adder having one input connected to the output of the first modulo-2 adder; and means for connecting the pseudo-random sequence of binary digits to said first n-stage shift register and to the other input of the second modulo-2 adder to derive at the latter''s output indicated error digits at effectively triple the true error rate; a corrector including a second n-stage shift register, a third modulo-2 adder connected to selected stages of said second n-stage shift register to replicate at the output of said third modulo-2 adder the binary input to said second n-stage shift register; a fourth modulo-2 adder having one input connected to the output of the second modulo-2 adder and the other input connected to the output of the third modulo-2 adder to derive at its output true error digits, the fourth modulo-2 adder being connected to the input of the second n-stage shift register.