Process and circuit arrangement for the measuring of the frequency of bit erros and block errors with optional block length in the transmission of binary coded data characters

Claim 3

The method defined in claim 1 wherein said generating step is accomplished using a shift register and comprising the additional steps of: setting said shift register to a predetermined base position prior to said adjusting step, resetting said shift register to said base position responsive to each error signal resulting from each said comparison, and preventing the return of said shift register to said base position upon the arrival of the end of said test text.

Claim 4

Apparatus for measuring block error rates in a receiving station of a binary coded data transmission system wherein a block test text signal having a predetermined number of bits is transmitted from a sending station to said receiving station, comprising: shift register means for generating a comparison signal having a predetermined text cycle length, timing means for controlling the switching operation of said shift register, synchronizing means for adjusting said comparison signal to be in phase with said test text signal, comparator means for comparing corresponding individual bits of said test text signal and said comparison signal and for producing an error signal upon determining a difference between said compared signals, first counter means, adjustable to have a maximum count corresponding to a desired block length, switching means for connecting said timing means to said counter means when said desired block length is of smaller duration than said text cycle length and for connecting an output from said shift register means to said counter means when said desired block length is of a duration greater than said text cycle length, said shift register delivering a pulse after each text cycle length, control means connected to said shift register means, said comparator means and said first counter means for, upon the completion of operation of said synchronizing means, establishing the exact sTarting and stopping times of the measuring operation, gating means for controlling the coupling of said error signal to an output terminal under the control of said first counter means, said gating means being open for the passage of an error signal only once during the desired maximum count period of said first counting means and second counter means for counting the error signals appearing at said output terminal.

Claim 5

Apparatus for measuring block error rates in a receiving station of a binary coded data transmission system wherein a block test text signal having a predetermined number of bits is transmitted from a sending station to said receiving station, comprising: shift register means for generating a comparison signal having a predetermined text cycle length, timing means for controlling the switching operation of said shift register, synchronizing means for adjusting said comparison signal to be in phase with said test text signal, comparator means for comparing corresponding individual bits of said test text signal and said comparison signal and for producing an error signal upon determining a difference between said compared signals, first counter means, adjustable to have a maximum count corresponding to a desired block length, switching means for connecting said timing means to said counter means when said desired block length is of smaller duration than said text cycle length and for connecting an output from said shift register means to said counter means when said desired block length is of a duration greater than said text cycle length, said shift register delivering a pulse after each text cycle length, control means connected to said shift register means, said comparator means and said first counter means for, upon the completion of operation of said synchronizing means, establishing the exact sTarting and stopping times of the measuring operation, gating means for controlling the coupling of said error signal to an output terminal under the control of said first counter means, said gating means being open for the passage of an error signal only once during the desired maximum count period of said first counting means and second counter means for counting the error signals appearing at said output terminal.

Claim 6

The apparatus defined in claim 2 wherein said shift register means includes adjustment means for adjusting said shift register to a predetermined base position and reset means for resetting said shift register to said base position responsive to each said error signal.