US4628507A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bit error detection circuit for PSK-modulated carrier wave
Assignee: NEC Corp
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Filing: 1984-04-12
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Granted: 1986-12-09
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Expires: 2004-04-12
Abstract
Abstract A bit errror detection circuit for checking the quality of a transmission path by accurately predicting a true bit error rate (BER) despite changes in the operating point of a non-linear element or fluctuations in the level of an input signal. An inputted PSK-modulated carrier wave is separately phase demodulated by a recovered carrier wave and a phase modulated carrier wave. These two phase demodulated PSK-modulated carrier waves are inputted into separate discriminator circuits 412 and 413 having a common discrimination level where the difference between the outputs can be compared by the comparator circuit 409 to predict a true BER.
Inventors
- 👤 Susumu Otani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:14
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2275; H04L1/00; H04L1/24; H04L1/241
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
178 words
A bit error detection circuit for a PSKmodulated carrier wave, comprising: carrier wave recovery means (403) for recovering a reference carrier wave of an inputted PSK modulated carrier wave; first demodulator means (405) responsive to the recovered reference carrier wave for phase-demodulating said input PSK carrier wave into a first demodulated signal; clock signal recovery means (411) for providing a clock signal in response to the first demodulated signal; oscillator means; modulator means (407) for phase-modulating the reference carrier wave with the output of the oscillator means (408); second demodulator means (406) responsive to the output of said modulator means for phase-demodulating the input PSK modulated carrier wave into a second demodulated signal; first discriminator means (412) for discriminating the first demodulated signal into a first digital signal in response to the clock signal; second discriminator means (413) for discriminating the second demodulated signal into a second digital signal in response to the clock signal; and comparator means (409) for comparing the first digital signal with the second digital signal to provide a pseudo bit error detection signal.
Claim 2
Dependent Claim
178 words
A bit error detection circuit for a PSKmodulated carrier wave, comprising: carrier wave recovery means (403) for recovering a reference carrier wave of an inputted PSK modulated carrier wave; first demodulator means (405) responsive to the recovered reference carrier wave for phase-demodulating said input PSK carrier wave into a first demodulated signal; clock signal recovery means (411) for providing a clock signal in response to the first demodulated signal; oscillator means; modulator means (407) for phase-modulating the reference carrier wave with the output of the oscillator means (408); second demodulator means (406) responsive to the output of said modulator means for phase-demodulating the input PSK modulated carrier wave into a second demodulated signal; first discriminator means (412) for discriminating the first demodulated signal into a first digital signal in response to the clock signal; second discriminator means (413) for discriminating the second demodulated signal into a second digital signal in response to the clock signal; and comparator means (409) for comparing the first digital signal with the second digital signal to provide a pseudo bit error detection signal.
Claim 3
Dependent Claim
180 words
A bit error detection circuit for a PSK-modulated carrier wave, comprising: carrier wave recovery means (403) for recovering a reference carrier wave of an inputted PSK modulated carrier wave; first demodulator means (405) responsive to the recovered reference carrier wave for phase-demodulating said input PSK carrier wave into a first demodulated signal; clock signal recovery means (411) for providing a clock signal in response to the input PSK modulated carrier wave; oscillator means; modulator means (407) for phase-modulating the reference carrier wave with the output of the oscillator means (408); second demodulator means (406) responsive to the output of said modulator means for phase-demodulating the input PSK modulated carrier wave into a second demodulated signal; first discriminator means (412) for discriminating the first demodulated signal into a first digital signal in response to the clock signal; second discriminator means (413) for discriminating the second demodulated signal into a second digital signal in response to the clock signal; and comparator means (409) for comparing the first digital signal with the second digital signal to provide a pseudo bit error detection signal.
Claim 4
Dependent Claim
180 words
A bit error detection circuit for a PSK-modulated carrier wave, comprising: carrier wave recovery means (403) for recovering a reference carrier wave of an inputted PSK modulated carrier wave; first demodulator means (405) responsive to the recovered reference carrier wave for phase-demodulating said input PSK carrier wave into a first demodulated signal; clock signal recovery means (411) for providing a clock signal in response to the input PSK modulated carrier wave; oscillator means; modulator means (407) for phase-modulating the reference carrier wave with the output of the oscillator means (408); second demodulator means (406) responsive to the output of said modulator means for phase-demodulating the input PSK modulated carrier wave into a second demodulated signal; first discriminator means (412) for discriminating the first demodulated signal into a first digital signal in response to the clock signal; second discriminator means (413) for discriminating the second demodulated signal into a second digital signal in response to the clock signal; and comparator means (409) for comparing the first digital signal with the second digital signal to provide a pseudo bit error detection signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-08 | 1990-06-09 | 1990-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-08 | 1994-06-09 | 1994-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-08 | 1998-06-09 | 1998-12-09 | $7700.00 | Window Closed / Lapsed |