Patent US4908328A successfully refreshed from Google Patents.
US4908328A
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High voltage power IC process
Assignee: Fairchild Semiconductor Corp
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Filing: 1989-06-06
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Granted: 1990-03-13
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Expires: 2009-06-06
Abstract
Abstract A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.
Inventors
- 👤 Chenming Hu
- 👤 Steven P. Sapp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:05
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/837; H10D84/839; H10W; H10W10/00; H10W10/10; H10W10/181; H10D84/40; H10D84/401; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/026; Y10S148/135
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
233 words
A process for forming high voltage transistors in a semiconductor wafer which will include low voltage conventional transistors, said process including the steps: starting with a first wafer of semiconductor material having a resistivity suitable for the fabrication of said low voltage transistors and a second wafer of semiconductor material having a resistivity that is substantially lower than that of said first wafer; forming at least one epitaxial layer of semiconductor material on one face of said second wafer; polishing a face of said first wafer and the face of said epitaxial layer of said second wafer to produce flat mirror finishes thereon; forming an oxide on each wafer on said polished faces; washing said oxide coated wafer faces to render them hydrophilic; placing said hydrophilic faces together to produce adhesion between said first and second wafers; heating said adhered wafers to coalesce said oxide coatings thereby to join said first and second wafers into a unitary structure; grinding and etching said exposed face of said first wafer until a predetermined thickness thereof remains; etching a groove in said first wafer that extends through it and through said oxide that joins said wafers together to expose a portion of said epitaxial layer; backfilling said groove with epitaxially deposited semiconductor material; shaping the exposed surface of said first wafer for subsequent planar processing; and forming a high voltage transistor in said backfilled semiconductor material.
Claim 2
Dependent Claim
233 words
A process for forming high voltage transistors in a semiconductor wafer which will include low voltage conventional transistors, said process including the steps: starting with a first wafer of semiconductor material having a resistivity suitable for the fabrication of said low voltage transistors and a second wafer of semiconductor material having a resistivity that is substantially lower than that of said first wafer; forming at least one epitaxial layer of semiconductor material on one face of said second wafer; polishing a face of said first wafer and the face of said epitaxial layer of said second wafer to produce flat mirror finishes thereon; forming an oxide on each wafer on said polished faces; washing said oxide coated wafer faces to render them hydrophilic; placing said hydrophilic faces together to produce adhesion between said first and second wafers; heating said adhered wafers to coalesce said oxide coatings thereby to join said first and second wafers into a unitary structure; grinding and etching said exposed face of said first wafer until a predetermined thickness thereof remains; etching a groove in said first wafer that extends through it and through said oxide that joins said wafers together to expose a portion of said epitaxial layer; backfilling said groove with epitaxially deposited semiconductor material; shaping the exposed surface of said first wafer for subsequent planar processing; and forming a high voltage transistor in said backfilled semiconductor material.
Claim 3
Dependent Claim
24 words
The process of claim 1, wherein said step of forming at least one epitaxial layer includes the deposition of a plurality of epitaxial layers.
Claim 4
Dependent Claim
19 words
The process of claim 1 wherein said grinding and etching step removes a major portion of said first wafer.
Claim 5
Dependent Claim
21 words
The process of claim 3 wherein the remaining thickness of said first wafer is on the order of a few microns.
Claim 6
Dependent Claim
26 words
The process of claim 1 wherein said first wafer is provided with a high conductivity face by doping the face to be oxidized prior to oxidation.
Claim 7
Dependent Claim
25 words
The process of claim 5 wherein said doping involves a slow diffusing impurity having the same doping conductivity type as that of said first wafer.
Claim 8
Dependent Claim
102 words
The process of claim 1 wherein said step of forming a high voltage transistor includes the steps: diffusing an impurity into said backfilled material having an opposite conductivity characteristic to a first depth that is less than the final thickness of said first wafer to create a transistor base region; diffusing an impurity having the same conductivity characteristic as said backfilled material into said base region within the confines thereof and to a lesser depth to create a transistor emitter region; and providing contacts to said base and emitter regions and a contact to said second wafer to form a collector contact.
Claim 9
Dependent Claim
173 words
The process of claim 1 wherein said step of forming a high voltage transistor includes the steps: diffusing an impurity having an opposite conductivity type into said backfilled material to a first depth that is less than the final thickness of said first wafer to create a transistor channel region; diffusing an impurity having the same conductivity type as said backfilled material into said channel region within the confines thereof and to a lesser depth to create a a transistor source region; forming a gate oxide that overlaps the channel region that exists between the edge of channel diffusion and the source diffusion; forming a gate conductor over said gate oxide thereby to provide a transistor gate; forming a metal contact to both said source and said channel regions outside the confines of said gate whereby said source is contacted and shorted to said channel thereby to form a transistor source combined with a transistor back gate contact; and forming a contact to said second wafer thereby to provide a transistor drain electrode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-03-12 | 1993-09-11 | 1994-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-12 | 1997-09-11 | 1998-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-12 | 2001-09-11 | 2002-03-13 | $7700.00 | Window Closed / Lapsed |